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AD4134 Multi-Device Synchronisation

Category: Datasheet/Specs
Product Number: AD4134

Hi,

I am looking for some clarification regarding synchronisation of 8 AD4134 devices with common MCLK and common ODR signals.

I note in the datasheet that a DIG_IF_RESET is required to ensure device-to-device synchronisation. It is not clear what ODR or DCLK should be doing when we apply this reset. Or indeed whether there needs to be a defined relationship between ODR and the SPI broadcast to all devices.

We are seeing very mixed results operating the ADC at 1 MSPS. A large proportion of captures seem to be out of phase by an entire ODR clock period, that is some chips are in one phase while the rest are in another (see attached plots sampling rising edge of square wave).

A DIG_IF_RESET is applied between the shots in the attached PDF. This reset is applied by a hardware process, after the falling edge of ODR, and consists of an SPI write to reg 0x01 with data equal to 0x82. The ADC is constantly sampling throughout, (constant ODR and gated DCLK).

Any further guidance you can provide would be much appreciated.

Regards,

S Robson

PDF

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  • hi S Robson

    Apologies for coming back late.

    i presume that you are operating the devices in High Performance, ASRC mode(ODR Input) with DCLK gated as input. 

    the DIG_IF_RESET command needs to be simultaneous to all devices and should be given once the PLL is locked.

    Please also check if PLL unlocks when you see that 1 ODR difference. Let me know how it goes.

    thanks

  • Hi folks,

    Apologies for the delay. I missed the forum notification.

    We are operating all the ADCs in :
    • ASRC Slave mode
    • SPI Control Mode
    • DCLK gated mode, INPUT, 50 MHz
    • 16-bit mode
    • High-Performance mode
    • Sinc3 filter with a sample rate of 1 MHz (or 850 kHz when we include the CRC and status bits for debug).

    Janine, here is the updated signal trace including the DCLK.

    Wa$im, you can also see that I have included the PLL Lock in pink.

    I have dropped the sample rate to 850 kHz so that I can include the CRC and status bits in the data word, and see the status of the PLL on every sample.

    Then I can look for my lock signal ever being "not equal" to ffff. Once we've established ODR the lock never drops.

    We also had a conversation yesterday with one of your local Apps engineers who may share further details with you once I provide an updated report.

    Thanks,

    Scott

  • Hi Rob

    can you confirm you are giving the simultaneous DIG_IF_RST post the PLL Lock?

    also i count 48 DCLK's between ODR pulses - Please let me know the Frame Size. Actually a dump of all registers would be great

    thanks

Reply Children
  • Yes, the PLL is locked long before we attempt the DIG_IF_RESET.

    You can see this in our ADC_PLL_LOCK register. This is updated at the end of every data shift using bit6 in the Data Interface Status from the chip.

    Should we be applying the DIG_IF_RESET after PLL lock and BEFORE we've sent any DCLKs to the device???

    48 clocks. Yes, we're only using two of the DOUTx lines and including the status and CRC in the data quantity. Reg 0x12 is equal to 0x01. And reg 0x11 is equal to 0x10

    Here's a full register dump for all of the chips :

    - - - - - - - - - - - - chip:A - - - - - - - - - - - -  - - - - - - - - - - - - chip:E - - - - - - - - - - - -
    | 00: 18 80 f1 07 9d 37 00 02 00 00 00 02 56 04 00 00 | | 00: 18 80 f1 07 8d 25 00 02 00 00 00 02 56 04 00 00 |
    | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 | | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 |
    | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 | | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 |
    | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a5 | | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bb |
    | 40: 00 0f 00 00 00 00 00 00 00 10 10 10 10 10 10 10 | | 40: 00 0f 00 00 00 00 00 00 00 14 14 14 14 14 14 14 |
     - - - - - - - - - - - - chip:B - - - - - - - - - - - -  - - - - - - - - - - - - chip:F - - - - - - - - - - - -
    | 00: 18 80 f1 07 1f 23 00 02 00 00 00 02 56 04 00 00 | | 00: 18 80 f1 07 d6 27 00 02 00 00 00 02 56 04 00 00 |
    | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 | | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 |
    | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 | | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 |
    | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ab | | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c1 |
    | 40: 00 0f 00 00 00 00 00 00 00 11 11 11 11 11 11 11 | | 40: 00 0f 00 00 00 00 00 00 00 15 15 15 15 15 15 15 |
     - - - - - - - - - - - - chip:C - - - - - - - - - - - -  - - - - - - - - - - - - chip:G - - - - - - - - - - - -
    | 00: 18 80 f1 07 66 2a 00 02 00 00 00 02 56 04 00 00 | | 00: 18 80 f1 07 36 53 00 02 00 00 00 02 56 04 00 00 |
    | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 | | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 |
    | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 | | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 |
    | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0 | | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c6 |
    | 40: 00 0f 00 00 00 00 00 00 00 12 12 12 12 12 12 12 | | 40: 00 0f 00 00 00 00 00 00 00 16 16 16 16 16 16 16 |
     - - - - - - - - - - - - chip:D - - - - - - - - - - - -  - - - - - - - - - - - - chip:H - - - - - - - - - - - -
    | 00: 18 80 f1 07 8d 29 00 02 00 00 00 02 56 04 00 00 | | 00: 18 80 f1 07 49 44 00 02 00 00 00 02 56 04 00 00 |
    | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 | | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 |
    | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 | | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 |
    | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b5 | | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cb |
    | 40: 00 0f 00 00 00 00 00 00 00 13 13 13 13 13 13 13 | | 40: 00 0f 00 00 00 00 00 00 00 17 17 17 17 17 17 17 |

    Thanks,
    Scott
  • thanks Scott

    ODR = 850 kHz, and Frame Size is 48. As per Pg 72

    ODR Time > tDCLK × Frame Size + 6 × tDCLK or tDIGCLK (whichever is higher)

    As per this formulae the Max ODR supported is 825k.

    incase not tried already can you reduce the ODR and see if it helps? also pull DCLK lower to check.

    thanks

  • So we double the 6? Because we're doing 2 channels per lane?

    Ok I'll give that a try and get back to you.

  • Also, should the ERR_DCLK flag not set if the rate is unsupported?

    Thanks,

    Scott

  • Signal trace with ODR running at 825 kHz. PLL remains locked but still seeing a 1 sample ODR error on some data captures

    Is there anything else I could monitor to help diagnose?

  • Hi Scott

    Apologies for coming back late, there is one experiment to check if DCLK is causing any issue.

    Steps are

    1. configure all SPI registers as per Need

    2. Start the ODR only (Not DCLK) and wait for the PLL to lock

    3. once PLL locks, Provide the DIG_IF_RST simultaneously to all devices.

    4. Start DCLK

    thanks

  • I am still looking at this after a few days vacation. I will have a further update tomorrow

    Thanks,

    Scott

  • Hi,

    Well this is new behaviour.

    We can't tell if the PLL is locked from the data word without the DCLK running, so I am relying on the software SPI registers to tell me that we have initial LOCK on the PLLs after boot.

    Then when we apply the DIG_IF_RESET, we get a couple of cycles where the chip report PLL LOCKED before losing lock and re-establishing LOCK a few cycles later. Is this expected behaviour? Perhaps this has been the source of our problem all along but previously I do not think I was seeing LOCK drop at any time.

    Thanks,

    Scott

  • Can you comment on whether the PLL unlocking after a DIG_IF_RESET is expected behaviour?

  • No, this is not the expected behavior. the blocks are different so PLL should not Unlock.

    PLL can only unlock incase of a config change or ODR change