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AD4134 Multi-Device Synchronisation

Category: Datasheet/Specs
Product Number: AD4134


I am looking for some clarification regarding synchronisation of 8 AD4134 devices with common MCLK and common ODR signals.

I note in the datasheet that a DIG_IF_RESET is required to ensure device-to-device synchronisation. It is not clear what ODR or DCLK should be doing when we apply this reset. Or indeed whether there needs to be a defined relationship between ODR and the SPI broadcast to all devices.

We are seeing very mixed results operating the ADC at 1 MSPS. A large proportion of captures seem to be out of phase by an entire ODR clock period, that is some chips are in one phase while the rest are in another (see attached plots sampling rising edge of square wave).

A DIG_IF_RESET is applied between the shots in the attached PDF. This reset is applied by a hardware process, after the falling edge of ODR, and consists of an SPI write to reg 0x01 with data equal to 0x82. The ADC is constantly sampling throughout, (constant ODR and gated DCLK).

Any further guidance you can provide would be much appreciated.


S Robson


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  • Hi Janine,

    Thanks for looking into this.

    I should clarify. We are sampling at 1 MHz and the phase difference we're seeing is in the order of an entire sample clock (i.e. 1us). I don't think an error this large can be attributed to tracking delays. However, to give more details, the 8 ADCs do not span more than 6 centimetres from the driving device

    I am more concerned that we are not performing the DIG_IF_RESET in the correct way. I have attached a signal trace so that you can see the relationship between the SPI write and the ODR pulse.

    We are assuming that it is the relationship of the reset with ODR which is more important, rather than DCLK for chip to chip synchronisation and an error which is measured in ODR periods.



  • Hi Janine,

    Is there anything further you can contribute on this?



  • Hi Scott,

    Apologies for getting back to you just now. Can you include DCLK in the signal trace? Please note DIG_IF_RESET should be issued simultaneously to all devices after ODR and DCLK.