AD4134 Multi-Device Synchronisation

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Hi srobson ,

We are looking into this and will get back to you.

Thanks,

Janine

Hi srobson ,

Can you help provide additional details on your setup and the schematic layout for the 8 ADCs?

Please note that the connection from the controller to the 8 AD4134 devices should be identical since a small layout mismatch could result in a phase mismatch.

Thanks,

Janine

Hi Janine,

Thanks for looking into this.

I should clarify. We are sampling at 1 MHz and the phase difference we're seeing is in the order of an entire sample clock (i.e. 1us). I don't think an error this large can be attributed to tracking delays. However, to give more details, the 8 ADCs do not span more than 6 centimetres from the driving device

I am more concerned that we are not performing the DIG_IF_RESET in the correct way. I have attached a signal trace so that you can see the relationship between the SPI write and the ODR pulse.

We are assuming that it is the relationship of the reset with ODR which is more important, rather than DCLK for chip to chip synchronisation and an error which is measured in ODR periods.

Thanks,

Scott

Hi Janine,

Is there anything further you can contribute on this?

Thanks,

Scott

Hi Scott,

Apologies for getting back to you just now. Can you include DCLK in the signal trace? Please note DIG_IF_RESET should be issued simultaneously to all devices after ODR and DCLK.

Thanks,

Janine

hi S Robson

Apologies for coming back late.

i presume that you are operating the devices in High Performance, ASRC mode(ODR Input) with DCLK gated as input. 

the DIG_IF_RESET command needs to be simultaneous to all devices and should be given once the PLL is locked.

Please also check if PLL unlocks when you see that 1 ODR difference. Let me know how it goes.

thanks

Hi folks,

Apologies for the delay. I missed the forum notification.

We are operating all the ADCs in :
• ASRC Slave mode
• SPI Control Mode
• DCLK gated mode, INPUT, 50 MHz
• 16-bit mode
• High-Performance mode
• Sinc3 filter with a sample rate of 1 MHz (or 850 kHz when we include the CRC and status bits for debug).

Janine, here is the updated signal trace including the DCLK.

Wa$im, you can also see that I have included the PLL Lock in pink.

I have dropped the sample rate to 850 kHz so that I can include the CRC and status bits in the data word, and see the status of the PLL on every sample.

Then I can look for my lock signal ever being "not equal" to ffff. Once we've established ODR the lock never drops.

We also had a conversation yesterday with one of your local Apps engineers who may share further details with you once I provide an updated report.

Thanks,

Scott

Hi Rob

can you confirm you are giving the simultaneous DIG_IF_RST post the PLL Lock?

also i count 48 DCLK's between ODR pulses - Please let me know the Frame Size. Actually a dump of all registers would be great

thanks

Yes, the PLL is locked long before we attempt the DIG_IF_RESET.

You can see this in our ADC_PLL_LOCK register. This is updated at the end of every data shift using bit6 in the Data Interface Status from the chip.

Should we be applying the DIG_IF_RESET after PLL lock and BEFORE we've sent any DCLKs to the device???

48 clocks. Yes, we're only using two of the DOUTx lines and including the status and CRC in the data quantity. Reg 0x12 is equal to 0x01. And reg 0x11 is equal to 0x10

Here's a full register dump for all of the chips :

- - - - - - - - - - - - chip:A - - - - - - - - - - - -  - - - - - - - - - - - - chip:E - - - - - - - - - - - -
| 00: 18 80 f1 07 9d 37 00 02 00 00 00 02 56 04 00 00 | | 00: 18 80 f1 07 8d 25 00 02 00 00 00 02 56 04 00 00 |
| 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 | | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 |
| 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 | | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 |
| 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a5 | | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bb |
| 40: 00 0f 00 00 00 00 00 00 00 10 10 10 10 10 10 10 | | 40: 00 0f 00 00 00 00 00 00 00 14 14 14 14 14 14 14 |
 - - - - - - - - - - - - chip:B - - - - - - - - - - - -  - - - - - - - - - - - - chip:F - - - - - - - - - - - -
| 00: 18 80 f1 07 1f 23 00 02 00 00 00 02 56 04 00 00 | | 00: 18 80 f1 07 d6 27 00 02 00 00 00 02 56 04 00 00 |
| 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 | | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 |
| 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 | | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 |
| 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ab | | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c1 |
| 40: 00 0f 00 00 00 00 00 00 00 11 11 11 11 11 11 11 | | 40: 00 0f 00 00 00 00 00 00 00 15 15 15 15 15 15 15 |
 - - - - - - - - - - - - chip:C - - - - - - - - - - - -  - - - - - - - - - - - - chip:G - - - - - - - - - - - -
| 00: 18 80 f1 07 66 2a 00 02 00 00 00 02 56 04 00 00 | | 00: 18 80 f1 07 36 53 00 02 00 00 00 02 56 04 00 00 |
| 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 | | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 |
| 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 | | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 |
| 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0 | | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c6 |
| 40: 00 0f 00 00 00 00 00 00 00 12 12 12 12 12 12 12 | | 40: 00 0f 00 00 00 00 00 00 00 16 16 16 16 16 16 16 |
 - - - - - - - - - - - - chip:D - - - - - - - - - - - -  - - - - - - - - - - - - chip:H - - - - - - - - - - - -
| 00: 18 80 f1 07 8d 29 00 02 00 00 00 02 56 04 00 00 | | 00: 18 80 f1 07 49 44 00 02 00 00 00 02 56 04 00 00 |
| 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 | | 10: 02 10 01 00 00 01 40 00 00 72 b7 ce 2b 00 aa 00 |
| 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 | | 20: 00 ff 00 00 01 28 00 00 00 00 00 00 00 00 00 00 |
| 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b5 | | 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cb |
| 40: 00 0f 00 00 00 00 00 00 00 13 13 13 13 13 13 13 | | 40: 00 0f 00 00 00 00 00 00 00 17 17 17 17 17 17 17 |

Thanks,
Scott