I am looking for some clarification regarding synchronisation of 8 AD4134 devices with common MCLK and common ODR signals.
I note in the datasheet that a DIG_IF_RESET is required to ensure device-to-device synchronisation. It is not clear what ODR or DCLK should be doing when we apply this reset. Or indeed whether there needs to be a defined relationship between ODR and the SPI broadcast to all devices.
We are seeing very mixed results operating the ADC at 1 MSPS. A large proportion of captures seem to be out of phase by an entire ODR clock period, that is some chips are in one phase while the rest are in another (see attached plots sampling rising edge of square wave).
A DIG_IF_RESET is applied between the shots in the attached PDF. This reset is applied by a hardware process, after the falling edge of ODR, and consists of an SPI write to reg 0x01 with data equal to 0x82. The ADC is constantly sampling throughout, (constant ODR and gated DCLK).
Any further guidance you can provide would be much appreciated.