My hardware goes to a steady state of 0 output conversions.
I have a +/- 2.5 V connection and the logic to 0 and -2.5V. SPI is connected through a level converter from 3.3V.
CS is fixed low and reset is high. After voltages are started up and SYNC_IN has rised, after 50 µs I start following:
0xAD00 reset
wait 240 µs, During this time DRDY pulses are coming at 27 kHz.
After a DRDY pulse, a SYNC_IN low pulse is done.
0x006C to enter SPI control.
0x1522 POWER_CLOCK, MCLK_DIV/4, PWRMODE-med
0x1653 Analog, unbuff, unbuff, AIN+ prech disabled, AIN- prech disabled
0x290F ADC_DIAG_ENABLE, Reference, Filter sat, Filter not settled, ext clock
0x1941 DIGITAL_FILTER, FIR filter, decimate 64
readings to check communication
0x5400 0000
0x5500 0000
0x5600 0000
0x5800 0000
0x5900 0041
0x6800 0010
0x6900 000F
0x6A00 000D
0x6D00 0085 MASTER_STATUS, Master error, Filter not settled
0x6E00 0000
0x6F00 0002 ADC_DIAG_STATUS, Filter not settled
0x7000 0000
0x7100 0049
0x6400 0055 GAIN_HI
0x1411 INTERFACE_FORMAT, STATUS_EN, EN_CONT_READ
then I wait for the DRDY goes high and then gives the negative sync pulse.
After 150 µs there is 2 DRDY pulses with data 0xE62A1084 and 0x0569A184.
They are 76 µs from each other, corresponding to 13 kHz.
And then it is 190 µs to the next DRDY pulse and they then DRDY repeat at a rate of 27 kHz with no data.
What is wrong?
