AD4134 SPI Timings

I am trying to configure the AD4134 in 4-Wire SPI Control Mode with an ESP32-S3. After studying the documentation in detail there are still some questions left open especially regarding SPI timings. The "Virtual Eval" tool also did not provide the necessary information, eventhough it's a great help.

Setup:

• ESP32-S3 (3.3V) connected via TXB0104 (4-Bit Bidirectional Voltage-Level Translator) to the AD4134 (1.8 V)
  • FORMAT0 => CS
  • FORMAT1 => SCL (@1 MHz)
  • DEC3 => MISO
  • DEC2 => MOSI
• For measurements a logic-analyzer as well as an oscilloscope (50 MHz bandwidth) is connected to each line (CS, SCL, MISO, MOSI). To make sure the Voltage-Level-Translator works properly, the logic analyzer is hooked up on both sides of the TXB0104.

Questions:

1. According to the documentation "In SPI Control Mode 0, the SCLK idles low, the falling edge of the SCLK is the driving edge, and the rising edge of the SCLK is the sampling edge. The output data on the SDO pin is clocked out on the falling edge of SCLK and the input data on the SDI pin is sampled on the rising edge of SCLK." For me this sound like CPHA1 for MOSI and CPHA0 for MISO. Is it correct that the AD4134 uses this non-standard SPI implementation?
2. In various diagrams a "[STATUS]" Byte is mentioned, which the AD4134 transmits on MISO while the ADDRESS is set on MOSI (Fig. 111). Could you provide information about this register such as in the chapter "Register Details"?
3. According to the documentation: "Because the FORMAT0/CS pin and FORMAT1/SCLK pin are read on power-up of the AD4134 and the device remains in this output configuration, this function must always be hardwired and cannot be altered dynamically. Figure 90 and Figure 91 show the formatting configuration for the digital output pins on the AD4134." Is this also valid in SPI Control Mode? If yes: are pull-up resistors during startup sufficient?
4. What is the minimum and maximum delay between pulling CS low and the first rising flank of SCL? The ESP32-S3 hardware SPI controller has basically no delay between those two events. With reduced functionalities a delay can be set in multiples of full SCL periods.
5. Could you provide a detailed diagramm with SPI Timings including minimum/maximum durations/delays?
6. Is there a special order that has to be considered when writing the registers?

I attached two screenshots trying to write and subsequently read the INTERFACE_CONFIG_A register. I get the following results, which do not seem right to me. After writing 00010000 I would expect reading 00010000 (or 00011000 with mirror bit). Furthermore the STATUS byte changed from 00000000 to 10000000 (or 11000000 depending on the correct CPHA setting).

• WRITE:

• READ:

Could you comment on possible reasons for this behaviour?

I hope some expert from Analog can help out with those questions. Thanks in advance.

Kind regards,

Patrick