I am evaluating the AD4001 for use in a new product. I have the EVAL-AD400x-FMCZ powered from its 12V input, connected to some custom logic, and fed test signals from a two-channel arb gen. SDI is tied to VDDIO, to use the chip in "!CS mode without busy indicator" per fig. 55 in the datasheet. I have followed the Troubleshooting section of the user guide and all of the voltages on the board are correct.
After clocking out a few bits from SDO (up to about 7 or 8 bits) SDO enters a weird high-impedance mode where some or all of the remaining bits are high-Z.
I have biased SDO to a half-VDDIO voltage with a 2.2k resistor so the high-Z states are easier to see.
When CNV goes high SDO goes high-Z, and when it falls the MSB (presumably) is present on SDO. This is correct. However, part way through the SPI transaction, weird high-Z bits creep in which surely can't be right.
The string of most significant bits seem to change as a block; 1111110z0z0z, for example, or 000000z0z0z0z, which may be indicative of 2's complement action, but there is never any activity in the least significant byte - it's always zero, with a few floaty high-Z's thrown in, even with very small mV changes in input voltage.
Anyone got any ideas?