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AD4001(EVAL-AD400x-FMCZ) SPI communication corruption / high impedance weirdness

Category: Hardware
Product Number: AD4001

Hi

I am evaluating the AD4001 for use in a new product. I have the EVAL-AD400x-FMCZ powered from its 12V input, connected to some custom logic, and fed test signals from a two-channel arb gen. SDI is tied to VDDIO, to use the chip in "!CS mode without busy indicator" per fig. 55 in the datasheet. I have followed the Troubleshooting section of the user guide and all of the voltages on the board are correct.

After clocking out a few bits from SDO (up to about 7 or 8 bits) SDO enters a weird high-impedance mode where some or all of the remaining bits are high-Z.

I have biased SDO to a half-VDDIO voltage with a 2.2k resistor so the high-Z states are easier to see.

When CNV goes high SDO goes high-Z, and when it falls the MSB (presumably) is present on SDO. This is correct. However, part way through the SPI transaction, weird high-Z bits creep in which surely can't be right.

The string of most significant bits seem to change as a block; 1111110z0z0z, for example, or 000000z0z0z0z, which may be indicative of 2's complement action, but there is never any activity in the least significant byte - it's always zero, with a few floaty high-Z's thrown in, even with very small mV changes in input voltage.

Anyone got any ideas?

Best,

Jeff

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  • Hi Jeff,

    Thanks for sharing this info. I have a couple of follow up questions:

    • What board are you using for your custom logic? Are you connecting to the AD4001 through the board's FMC connector? Or are you using fly-wires from some other board?
    • What is the source for the AD4001's VIO supply? Is it the default +3.3V supplied by on-board U4 (ADP7118)? Or are you supplying it in from your controller board?
    • What is the voltage on IN+ and what is the voltage on IN- when you read these results back? If the "z's" in those codes were "1s", would those codes match expected values based on your input voltage?
      Note, I'm asking for absolute voltage on each IN+ and IN- pin, not the differential voltage between the two - the reason being is to double check the common mode input voltage requirement is being maintained.
    • Is there any possibility that there's other sources of contention on the SDO line? Do you have any other components sharing the SPI bus with the AD4001 in your custom logic/board?

    Thanks,

    Tyler

  • I now have the circuit working properly with the oscilloscope probes disconnected. The solution was to add 82R series source termination resistors at the input end of the SPI signals between the logic board and EVAL-AD4001-FMCZ, i.e. a resistor at the SCK and CNV outputs of the logic board where they drive the flying wires to the EVAL board, and a resistor at the output of the EVAL board on the SDO line where it drives the returning wire.

    Other values of resistor worked too - I did a little optimisation to slow the slew rates a bit without making the clock periods unduly narrow.

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  • I now have the circuit working properly with the oscilloscope probes disconnected. The solution was to add 82R series source termination resistors at the input end of the SPI signals between the logic board and EVAL-AD4001-FMCZ, i.e. a resistor at the SCK and CNV outputs of the logic board where they drive the flying wires to the EVAL board, and a resistor at the output of the EVAL board on the SDO line where it drives the returning wire.

    Other values of resistor worked too - I did a little optimisation to slow the slew rates a bit without making the clock periods unduly narrow.

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