Hi All,
Testing out a fairy straight forward setup here. But its failing to communicate with master.
according to datasheet
With SDI high, a rising edge on CNV initiates a conversion, selects CS mode, and forces SDO to high impedance.
But when i check the SDO/MISO is always pulled low.
Any insights will be appreciated.
Thanks
Good day.
As you have said, with SDI = HIGH, a rising edge on CNV initiates a conversion. I’m assuming this is what you mean by the “PULLED HIGH” at the CNV pin on your setup.
During the start, the SDO is forced to HIGH IMPEDANCE. It appears to be pulled low since we are still at the start and no data is read yet.
During acquisition, CNV = PULLED LOW, the MSB is output in the SDO, and this is the data that we can see there.
The SDO returns to the HIGH IMPEDANCE state after acquisition, and it will follow the last bit that we got during the acquisition. So, if the output of the last bit of the data is low, it follows this value (as seen in the attached captures). Same goes when the last bit of the data is high.
Hope this helps!
Hello! If we pull both SDI and CNV to high during the idle state (without conversion/acquisition), SDO will also be driven high — since the conversion result is output on this pin.
You may see this attached capture for your reference (measurements are at the lower left part).
Hello! If we pull both SDI and CNV to high during the idle state (without conversion/acquisition), SDO will also be driven high — since the conversion result is output on this pin.
You may see this attached capture for your reference (measurements are at the lower left part).
