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AD7771 Recommended for New Designs
The AD7771 is an 8-channel, simultaneous sampling analog-to-digital converter (ADC). Eight full Σ-Δ ADCs are on-chip. The AD7771 provides an ultralow...
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AD7771 Phase Adjustment Question

		
	
				

			

									
					    BolinQ
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Jun 23, 2022 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user is experiencing issues with phase adjustment on the AD7771 ADC when setting different CHx_SYNC_OFFSET values. The final answer suggests setting the channel with the largest phase delay (CH1 in this case) to 0, and adjusting the other channels relative to it. The decimation rate is 32, and the phase delay must be less than this value. The user confirms that setting CH3 to 0 and adjusting other channels works, but Ia and Ic only function correctly with 0 or 31.
                        	    

                
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Category: Software

    		        		            		    
Product Number:  AD7771 

    		        		        		        
Software Version: CCES

    		    		    

		    		    
		    			

			    
Hi everyone, 


I am new in DSP. I have a problem when programming the AD7771. 


I was trying to use phase adjustment for each ADC. However, the function only works when I set all CHx_SYNC_OFFSET with same number, other wise only smallest one work. 


for example: my Decimation Rate = 32. 


                     the function will work for all ADC if i make CH(0-7)_SYNC_OFFSET = 17(0x11); 


                     if I set eg: CH(3)_SYNC_OFFSET = 16 and maintain rest of them equal to 17. Only CH3 will do phase adjustment. However, when i check the data in each channels they give me correct data which means I have successfully wrote the data to each registers. 




I also have hard time to understand "Phase Adjustment" part in Data Sheet. 


                . "In other words, programming the channel with higher phase delay as CHx_SYNC_OFFSET= 0, any other channel with lower phase, can be delayed to compensate for the phase mismatch."[p.42]


I am not sure is this the reason only smaller number in register can work? 


 


best regards,


Bolin                  

			

			
									
		                             
                        

    

                                            
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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Jun 27, 2022 6:09 AM
            
            
						
			            		
    
		
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    Hi Bolin,
    

    

    If you write the same number to all the SYNC_OFFSET you will see the same phase delay in all the signals so the effect will be like doing nothing.
    

    The phase delay must be relative to the at least one channel (normally the one with has highest phase delay since it is the slowest). This channel must be configured with 0x0 phase delay and all the others will take that channel as a reference for their delays.
    

    As it is specified in the datasheet, the phase delay must always be lower than the decimation rate.
    

    I would recommend to set to 0 the channel with highest phase delay, play around with the value of SYNC_OFFSET of the other and plot the data to see if there is any change when the SYN_OFFSET is change.
    

    Regards
    

    Joan
    

    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Jun 27, 2022 5:04 PM
            
            
												
						in reply to JoanOrtega
					
										
			            		
    
		
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    Thanks Joan, 
    

    I should give more information about my case, I am working on Three phase power system. CH0-3 is current A to C and N, CH 4-6 is voltage. the data shows that CH1 which is Ib has largest phase delay. So I set CH3 = 0. I can change Va-Vc (Ch4-6) to any number and it gives me expected result. however, Ia and Ic can only be set to 0 or 31 other wise the output data will be wrong.
    

    hope I describe clearly. 
    

    

    Best regards,
    

    Bolin
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Jun 28, 2022 2:36 AM
            
            
												
						in reply to BolinQ
					
										
			            		
    
		
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    Hi Bolin,
    

    If channel CH1 has the largest phase delay, you should set this channel to 0, not CH3.
    

    In the previous comment you said that decimation rate was 32 so in that case the maximum phase delay that you can use is 31 so it seems to be working properly.
    

    Regards
    

    Joan
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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