AD652 FVC Stability

I am using the AD652 as a synchronous frequency-to-voltage converter in the FVC mode. I conducted a series of measurements of the output voltage (Vout) across a wide range of input frequencies (each of which was held constant for the duration of the measurement) and found that Vout experienced instabilities in particular regions of frequencies (each fluctuating in a periodic manner).

The bounds of these regions generally coincided with multiples of the clock frequency used (fclk = 2.5MHz), which led me to assume that the issue might have something to do with the timing in the logic circuit (AND gate, D-flop, D-latch -- on the bottom right).

The following graphs show the residuals associated with the linearity of the positive and negative slopes, where the residuals of the negative slopes are usually 3 orders of magnitude greater than those of the positive slopes.

Using no prescaler:

Using 64 prescaler:

I'd appreciate any help in understanding:

1. Why the Vout - Fin graph follows this jagged relation
2. Why the linearity and stability of voltages varies in a symmetric fashion
3. Is there any way of mitigating the instabilities in output voltage experienced

The following are measurements of the input signals:

The clock signal I obtained at pin 10 is as follows:

An example of an input frequency signal at pin 14 supplied by a MB506 wave generator (24MHz prior to 128 prescaler) is:

An example of the periodic fluctuations in output voltage experienced, measured at an input frequency of 10MHz (~78kHz after prescaler), displayed a repeating dip (with ~0.167s periodicity):

An example of a stable output voltage, measured at a 47MHz input frequency (~367kHz after 128 prescaler) is:

Taking a closer look at the theory of a charge-balance type VFC, I thought that having a shorter duty cycle might improve the stability of the output voltage. These are the output voltages and corresponding residuals in linearity I obtained over a range of duty cycles:

Could these behaviors be attributed to the hysteresis of the high speed comparator of the AD652 (particularly comparing the sinusoidal and 50% square wave inputs)?
Do you know what the hysteresis of this comparator is?