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AD4680: Is tQUIET always necessary for all the Fsclk?

Hi All,

I have two questions about AD4680.

1)  Is the tQUITE in Figure 2 always necessary over the entire SCLK frequency range? 

    I understand we need a tQUITE time when using 40MHz SCLK to make sure 1Msps throughput, is tQUITE(500ns)  still required for 10MHz SCLK operation?

2)  In Figure 3, It seems that tCONVERT and tACQUIRE overlap, is it true?

     If yes, The AD4680 starts the next sampling while it is still in conversion operation, could you tell me why it can be achieved?

Warm Regards,

Leo

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  • Hi,


    1. The tquiet is defined as the Interface quiet time before conversion, so this is the delay before it will have a new set of conversion or acquire time. This tquiet is required to all the frequency of the SCLK since this will make sure that the communication between the ADC and the microcontroller has ended and it is ready for a new set of conversion and acquisition.


    2. Acquisition time overlaps on the later part of the conversion is approximately 140ns to 160ns after the start of conversion because this feature is available for AD4680 in which this overlap achieves a longer acquisition time allowing much time for the input signal to settle. Longer acquisition time gives you a wider range of flexibility on changing the RC filters to a larger value that will result in a higher bandwidth and filters the high-frequency signal that will enter the ADC.


    Regards,
    Andrei

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  • Hi,


    1. The tquiet is defined as the Interface quiet time before conversion, so this is the delay before it will have a new set of conversion or acquire time. This tquiet is required to all the frequency of the SCLK since this will make sure that the communication between the ADC and the microcontroller has ended and it is ready for a new set of conversion and acquisition.


    2. Acquisition time overlaps on the later part of the conversion is approximately 140ns to 160ns after the start of conversion because this feature is available for AD4680 in which this overlap achieves a longer acquisition time allowing much time for the input signal to settle. Longer acquisition time gives you a wider range of flexibility on changing the RC filters to a larger value that will result in a higher bandwidth and filters the high-frequency signal that will enter the ADC.


    Regards,
    Andrei

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