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AD7682 Interface Timing

I am using the AD7682 in Read/Write Spanning Conversion mode without busy indicator (page 34 of datasheet). It mentions in this section that the first 15 SCK falling edges clock out the conversion results starting with MSB – 1. However, the timing diagram on the same page shows data out starting at MSB.

 Using my tools, I am getting 15 bits of data starting with MSB -1 down to LSB, so I assume that the timing diagram has a typo in the SDO line, and it should indicate MSB – 1 instead of MSB.

 Anyways, my question is, how do I read the MSB in the RSC mode without Busy Indicator?

Updated Subject and Added Tags for clarity
[edited by: @skowalik at 11:17 PM (GMT -5) on 9 Mar 2022]
  • Keith,

    The MSB is output on the falling edge of CNV + ten (that is immediately following conversion when the interface is enabled) in the configuration you are using and the MSB-1 is therefore clocked out on the first falling edge of the first clock that follows; assuming you are using a clock which idles low (CPOL=0 as shown in the diagram).   Thus is sounds like you need to add a 16th clock to your pattern to read in the LSB and then you should have a full 16-bit word.

    Give that a try and let us know if that doesn't work.  If it doesn't please share a scope or logic analyzer plot of what you are seeing with your setup and we'll try to help you figure out what's going on.


  • Hi Sean,

    Thanks for your response. Vref=5V. And here is what my data looks like when applying voltages ranging 0-5V. I have CFG[0]=0 so I am reading back the CFG after reading data output. Also I have the CFG configured so that data output corresponds to input at AI0 (no sequencing):

    data output is repeated starting at Midscale and higher input voltages. 

  • Keith,

    Okay so your data shows we're missing the MSB but I have no reference as to how you've configured your processor to communicate with the device.   Can you share your timing using an oscilloscope or Logic analyzer?   Make sure either one provides sufficient time resolution so that we can see the transition timing.

    A short description on the interface configuration in your processor would also be helpful.  For example how are you controlling CNV, is there sufficient setup time before you start clocking the interface, etc.   

    To me this looks like the interface just isn't loading the MSB in (rising edge of clock, CPOL=0) before the MSB to MSB-1 transition on the subsequent falling edge.   Are you sure there is sufficient time between the falling edge of CNV and when you start clocking (ten)?


  • Thanks a lot Sean, I have modified my model to take the first reading at the edge of CNV+ten and I finally get my missing MSB.

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