Regarding datasheet AD7760, Rev. A | Page 7 of 36, timing diagrams are shown for Data Read (Figure 2. Filtered Output—Parallel Interface Timing Diagram) and register write (Figure 3. AD7760 Register Write) I have some questions.
In both diagrams neither MCLK nor ICLK clock is shown. Does that mean it is an asynchronous interface and does not have any relation to MCLK, except that the clock restricts certain values to lower limits regarding t_ICLK? To be honest, I can't imagine that, but it might be possible.
Also Figure 43. AD7760 Modulator Output Mode (CDIV = 1) and (CDIV = 0, n is even) on Page 20 does show neither MCLK nor ICLK.
Regarding Figure 3, ist the timing for writing REGISTER DATA the same as REGISTER ADRESS?
Thanks in advance,