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AD7760 Interface Timing


Regarding datasheet AD7760, Rev. A | Page 7 of 36, timing diagrams are shown for Data Read (Figure 2. Filtered Output—Parallel Interface Timing Diagram) and register write (Figure 3. AD7760 Register Write) I have some questions.

Question #1:

In both diagrams neither MCLK nor ICLK clock is shown. Does that mean it is an asynchronous interface and does not have any relation to MCLK, except that the clock restricts certain values to lower limits regarding t_ICLK? To be honest, I can't imagine that, but it might be possible.

Also Figure 43. AD7760 Modulator Output Mode (CDIV = 1) and (CDIV = 0, n is even) on Page 20 does show neither MCLK nor ICLK.

Question #2:

Regarding Figure 3, ist the timing for writing REGISTER DATA the same as REGISTER ADRESS?

Thanks in advance,

Johannes Herzig

  • Hi, 

    1. The time the /DRDY pin will go low is of course dependent on ICLK or MCLK as the ODR is based on the ICLK frequency. The ADC is continuously converting and the ADC takes care of the timing that is why the user just need to monitor the /DRDY pin. I think the MCLK timing is more relevant if the user is planning to use the /RESET or the /SYNC pin to control the start of conversion or synchronize multiple ADCs for example as it requires to be synchronize with the MCLK. 

    2. If you meant minimum restriction yes I think so. 



  • Hi Jellenie,

    thanks for your reply.

    1.) You mentionend the "ODR". Does this stand for "Ouput Data Register"? Any register is a synchronous device regarding clocking in data. But the output might nevertheless work asynchronous, e.g. /RD/WR is an asynchronous output enable driving the ouput stage from HighZ to D. But switching between "DATA MSW" and "LSW + STATUS" requires at least a rising edge clock probably during t6 I asume. Thus it is a synchronous process.

    Can you confirm my assumption even the timing chart does not reflect that?

    Why did no one draw a clock signal into this chart?

    2.) To be more precise: Is /CS low during "REGISTER DATA" write cycle as long as t15 (4 times ti)?

    Best regards,


  • Hi,

    The "ODR" stands for Output Data Rate. It is the rate at which conversions are available on a single channel when the ADC is continuously converting. For the AD7760, The output data rate depends on the frequency of this MCLK. 



Reply Children
  • Hi Andrei,

    thanks for your comment - I did not consider this acronym interpretation but it completely makes sense.

    But some questions still remain open...

    I am currently designing the bus interface in an FPGA for two AD7760 sharing the same bus. For highest datarate I need to optimise the timing - thus my questions.



  • Hi Johannes, 

    Okay I think there is confusion here. The data conversion or DRDY is synchronous with ICLK/MCLK. However, like I said the ADC takes care of the timing, so the customer only needs to monitor the DRDY pin so the figure 2 or figure 43 did not show the MCLK/ICLK because the DRDY itself is enough to know when will the data is valid. But the modulator is of course running at ICLK rate and it depends on the filter configuration when will exactly the conversion of the equivalent word will be available. The table 6 for example shows the timing, but user do not really need to timeout this as the DRDY will time this out for you. As per /CS, /RD/WR these are input signal and the timing requirements to put these low after the DRDY goes low must also be met to access valid conversion. 

    As for the Figure 3 I think the ICLK is not drawn but the timing are mostly referred to ICLK, for example the RD/WR line is held high while the CS line is brought low for a minimum of four ICLK periods (t15). So writing the data to register address or data must meet this minimum requirements. 



  • Hi Jellenie,

    thank you for your answer so far. Okay, yes, I too think there is some confusion... :-)

    On one hand I am not a default english speaker and on the other hand there might have been a clash with my somehow oldschool technical vocabulary.

    I would not like a timing chart which represents synchronous signals without showing a clock or even figure out which clock edge the signals are sampled on. The only reason to do so is that the timing is asynchronous regarding clock and the parallel digital interface. Is that the case?

    If the answer is "Yes, it's asynchronous. Do not mind phase relation and frequency of the bus clock, you only have to guarante minimum times given in the specification. ", I would be completely satisfied.

    If the answer is "No, it's synchronous", I would expect to have some timing information related to clock edges, setup and hold times or the like. These are not given in the AD7760 datasheet, what led me to the assumption that the interface might be asynchronous - but nowhere it is explicitly written.

    I fully understand the DRDY signal and that the conversion process is synchronous to CLK (ICLK or MCLK) and that . My question refers to the interface only. The point is: an asynchronous interface is somehow unusual these days and it is not explictly written in the AD7760 datasheet. I searched for the word "asynchronous" in the PDF document and it is not present.

    For me it is now very clear, that the interface is what I would call asynchronous.