LTC2324-14Production
The LTC2324-14 is a low noise, high speed quad 14-bit + sign successive approximation register (SAR) ADC with differential inputs and wide input common...
Datasheet LTC2324-14 on Analog.com
Why do you mean by always? Does it means even when the device is powered down?
As a good practice we do not recommend to apply any analog or digital inputs when supplies are power off. May I know the reason for the asked? Is it not possible to disable the clock when the device is powered down?
However, I don't think it will potentially damage the part if the current input is very small. Do you know the current input at the clock pins? And what do you mean by power off like supply pins are floating or connected to GND?
On another thought. Does it means continuously supplying the SCLK even if you are not going to communicate (write or read)? I don't think that is also a good a practice. Excessive or incorrect number of SCLKs may affect synchronization of the interface. It may also be a cause of miscommunication.
Yes, I think you understand the point of my question.
It seems like it is not good to supply continuously SCLK even if not going to communicate(yes, LTC2324-14 also needs to be powered on in this case). I will use an FPGA to access LTC2324-14 and consider how to make and supply SCLK to LTC2324-14
So, as your recommendation, Supplying SCLK referring to CNV Signal is good, and do not supply a continuous SCLK, am I right?
