AD4695 no activity on SDO, always high-Z


We are currently developing a board using 3 AD4695BCPZ ADCs connected to the same SPI bus. We are experiencing an issue where no data is appearing on any of the SDO pins of the ADCs - all 3 SDO pins are connected onto a common MISO line but it remains undriven at all times despite read/write instructions sent on the SPI bus. 

The microcontroller used a Teensy 4.0 running at 3.3V. Inputs to the AD4695s are at 3.3V logic levels, which according to the datasheet p6 (Rev. 0) is within the working range of the device. The MISO line is attached to a 1.8V -> 3.3V level shifter.

The pin configurations on all 3 AD4695s are as follows.

AVDD:   3.3V
VDD:    1.8V
VIO:    1.8V
REF:    2.5V
RESET:  Tied to VIO
LDO_IN: Tied to GND

SDO:    Common MISO line to 1.8V -> 3.3V shifter
SDI:    Common MOSI line from MCU (3.3V)
SCK:    Common SCK line from MCU (3.3V)

CS:     Separate digital outputs from MCU (3.3V)
CNV:    Tied to CS


All of the above voltages have been measured at the pins of each AD4695 package and confirmed to be correct. Signals on the CS, SDI and SCK have also been probed at the package and confirmed to be present and correct. No shorting of any lines has been observed from current draw and thermal measurements.

An example of a test communication to read from the DEVICE_TYPE register is detailed below:

SPI settings: SCK = 1MHz, SPI_MODE_3 (CPHA=1, CPOL=1), MSB_FIRST

SPI_transfer(0x80); //read bit set, top 7 bits of address set to 0
SPI_transfer(0x03); //address of DEVICE_TYPE register
SPI_transfer(0x00); //padding
Set CS High;

This test is repeated for all 3 ADCs, only switching the CS pins as appropriate. The data pins of each ADC were probed at the IC package and verified. The CS pins were observed to transition low for the duration of the transaction, 3x8 pulses of SCK were seen, and the 3 bytes appeared correctly on the SDI pin clocked in at each rising edge of SCK. However, all SDO pins remain in a High-Z state at all times - only EMI is being picked up when probed.

At this point we are unsure what the issue could be, it would be great if you could provide some assistance on this. 

Best Regards

  • 0
    •  Analog Employees 
    on Sep 25, 2021 3:06 PM


    Thanks for your query and detailed description of the issue.

    This one is puzzling, as the AD4695 supply, etc. pin voltages and SPI transfers are all correct. A couple questions:

    1. Are VDD and VIO (+ RESET) shorted together and driven by the same source?

    2. Have you attempted a software reset prior to attempting a SPI read? If not, I would recommend doing so. This involves a SPI write of 0x90 to address 0x0000.



  • Hi Tyler,

    Thanks for your speedy reply. Responding to your questions:

    1. VDD, VIO and RESET are indeed shorted together and driven by a common 1.8V LDO.

    2. I've attempted a software reset on startup, with a 10ms delay before and after sending the instruction. There does not appear to be any change in the SDO behaviour. Quick question regarding soft reset - datasheet page 79 indicates that bit 0 as well as bit 7 should be set to trigger the reset (screenshot at end of message), which would be a write value of 0x91. Can you confirm whether this is correct? In any case I tested both 0x90 and 0x91 with no change SDO in behaviour seen.

    Please let me know if there's any more tests/info I can provide. We've been stuck on this issue for a while now, so your assistance is appreciated.

  • 0
    •  Analog Employees 
    on Sep 28, 2021 11:54 AM in reply to jli_elec

    My mistake, 0x91 is the correct code for the software reset.

    During your prototyping, have you ever tried only populating 1 out of the 3 AD4695s and seeing if SDO works then? You mentioned testing for contention between the 3 SDO pins but it might be a good check to see if there's any interaction there that isn't obvious. Hopefully that's not too painful to try given the LFCSP package.

    Do you have any individual control over the RESET pins for the devices? i.e. instead of tying them to VDD + VIO, tie them to a GPIO line, to try toggling it/them LOW instead of doing a software reset? Is that easy enough to try?

    In the meantime, I'll recreate your conditions on my setup and see if I can replicate the SDO behavior.

    Thanks for your patience,


  • 0
    •  Analog Employees 
    on Sep 30, 2021 11:59 AM in reply to jli_elec

    We recreated the supply + RESET setup described in your query and were unable to replicate the SDO issue. We were able to successfully read register and ADC data over SDO with VDD = VIO = RESET = 1.8V.

    I think the next thing to check is the load on the SDO line. I still recommend disconnecting all but one AD4695 SDO pin from the shared bus to see if there is some contention between the pins. I would also recommend disconnecting the level shifter from the bus temporarily, just to remove all loads from the AD4695's SDO pin.

    If the SDO pin ends up responding under these conditions, then we'd know there's some loading going on. If not, we'll reassess.