AD7770 Control

HI ,

In my application I need to switch the inputs  to the AD7770  after each conversion. During switching of the the input , AD7770 should be in idle state .Could you please  help me , which pins I  need to use to make AD7770 in idle state.

  • 0
    •  Analog Employees 
    on Aug 2, 2021 3:54 AM


    Apologies. I'm not sure if I understand the application. What do you mean by switch the inputs to the AD7770, does it mean you have another ADC in your system or the inputs are connected from a different circuitry? 

    And what exactly you mean by idle mode, it does mean that the ADC is not converting or the filter and modulator are held on reset state? The SYNC_IN pin is usually used if you wish to synchronize the conversions of multiple devices or to control the start of conversion. A pulse on the SYNC resets the digital filter, but the registers programmed are not affected. 

    At normal operation the SYNC_IN signal must be high, when a pulse signal is applied the digital filters will reset and resynchronized on the rising edge of the SYNC_IN signal. 

    If you are using the START and/or SYNC_IN inputs, then you should provide the sync through either of those inputs. 



  • Hi Jellenie ,

    Thanks for the Response .

    witch the inputs to the AD7770 - means that  inputs are connected from a different circuitry after each read.


    So , while doing the switching input to different  circuitry for ADC channel  ,we don't want the ADC to sample the data and drdy generation . How to control the drdy generation using the START signal


    I planning to use the START pin for synchronization and SYNC_OUT shall be loopback to SYNC_IN pin.

  • 0
    •  Analog Employees 
    on Aug 2, 2021 10:23 AM in reply to Arun871991

    Hi Arun,

    Note this is a free-running Sigma Delta ADC. So, if you switch the analog inputs, you will need to reset the digital filter every time you switch the inputs and you can use the START pin for that. Note that this way of operating the device means having to wait for the filter to settle on each sample, so the maximum ODR will probably be liimited.

    I wrote an article some tima ago about synchronising several AD777x, may not be 100% match to the topic but it talks about reseting the filter and so on. I hope it helps.

    Newest Sigma-Delta ADC Architecture Averts Disrupted Data Flow When Synchronizing Critical Distributed Systems | Analog Devices



  • 0
    •  Analog Employees 
    on Aug 5, 2021 10:44 AM in reply to Lluis

    BTW , would you mind letting us know the FPGA you are using on your design or if any FPGA development kit (Zedboard, Microzed, etc) during prototyping? Just for the record.