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AD7173 internal ADC master clock freuqency aging

Dear all

We use AD7173-8 on our new product, using ADC's internal master clock which is 2MHz, and there is a SMPS power module close to the ADC.The power module's switching frequecy varies from 1.9M to 2.3M. We find that some of boards using power module with about 2MHz switching frequency has some unexpected noise on ADC's output sample rate. We tried many ways such as slowing down the output data rate of AD7173, selcecting lower internal filter bandwidth, enabling internal buffer, or changing ADC's input filter loop parameters, all these are in vain. It seems that the power modules' Radiated Emission interferes with the AD7173's input pins, and the noise frequency is so close to ADC's master frequency that it has frequency aliasing. The newly generated frequency is too low to be filtered by AD7173's internal digital filter.

Now our product has no time to redesign PCB, so we will screen out the power modules which has frequency above 2.1MHz. But we want to know the aging performance of AD7173 intermal master clock, whehter its internal master clock will drift to 2.1MHz or not. Also can you help to provide the distribution of internal master frequency? We need to make assessment on this scheme---screen out the frequency of power module.