AD7173 internal ADC master clock freuqency aging

Dear all

We use AD7173-8 on our new product, using ADC's internal master clock which is 2MHz, and there is a SMPS power module close to the ADC.The power module's switching frequecy varies from 1.9M to 2.3M. We find that some of boards using power module with about 2MHz switching frequency has some unexpected noise on ADC's output sample rate. We tried many ways such as slowing down the output data rate of AD7173, selcecting lower internal filter bandwidth, enabling internal buffer, or changing ADC's input filter loop parameters, all these are in vain. It seems that the power modules' Radiated Emission interferes with the AD7173's input pins, and the noise frequency is so close to ADC's master frequency that it has frequency aliasing. The newly generated frequency is too low to be filtered by AD7173's internal digital filter.

Now our product has no time to redesign PCB, so we will screen out the power modules which has frequency above 2.1MHz. But we want to know the aging performance of AD7173 intermal master clock, whehter its internal master clock will drift to 2.1MHz or not. Also can you help to provide the distribution of internal master frequency? We need to make assessment on this scheme---screen out the frequency of power module.

Tks~

Parents
  • +1
    •  Analog Employees 
    on Jul 28, 2021 6:37 AM

    Hi, 

    I do not see any histogram data of internal master clock in the datasheet so I need to check within our team if we have plots to share with you. 

    I am curious about how you will screen out the said frequency? Are you somehow going to put a filtering in the AINs but I am not sure how because you have mentioned that the noise frequency present at the input is lower? May I know how low or what's the noise frequency present at the input due to power module noise? I'm sorry I'm just curious how are you planning to do this and how it relates to the internal clock accuracy? 

    Thanks,

    Jellenie

  • Hi Jellenie

    Thanks for your reply, I'll updater your questions separately.

    1. How you will screen out the said frequency?
    George_017: The power IC vendor provide the histogram of each wafer LOT which is 100% tested on final ATE, we use the one with higher switching frequency.

    2. How low or what's the noise frequency present at the input due to power module noise?
    George_017: We acquire the waveform on AD7173's AIN pins, there is around 1.2mV ~2MHz interfering noise which is the same as power IC's switching frequency. The AD7173's converting results show a leaping voltage as high as 0.9mV;
    when testing another board of which the power IC's frequency is around 2.1MHz, we can also see the same interfering noise on AIN pins (~2.1MHz 1.32mV), but AD7173's converting results have no jumping.

    3.How are you planning to do this and how it relates to the internal clock accuracy?
    George_017: We injected different frequency noise, the AD7173's output data returned normal when the injected frequency is above 2.1MHz;so we want to use power IC with higher frequency to avoid possible frequency aliasing.
    So we want to know AD7173's master clock histogram as well as master clock's aging trend, will the internal master clock frequency increase or decrease as the working time increases?

    Tks.

  • 0
    •  Analog Employees 
    on Jul 29, 2021 3:35 AM in reply to George_017

    Hi, 

    It is interesting because the analog input bandwidth of the ADC is much lower than the noise frequency. So my thinking is that a simple RC at the input could fixed this issue? 

    Thanks,

    Jellenie

  • 0
    •  Analog Employees 
    on Jul 29, 2021 3:55 AM in reply to George_017

    Anyways, in terms of your requested data.

    Like I said I'll check if we have those type of specific data especially the aging trend as we do not usually perform long term drift across all of our specs. We only have reliability testing to ensure that the part meets spec over its lifetime. You can check reliability data here. 

    Wafer Fabrication Data | Analog Devices

    If in any case we do not have or cannot provide the specific data, I guess a customer would need to measure this type of data themselves in their own system as the system drift is more relevant.

    Thanks,

    Jellenie

  • Hi Jellenie

    We've already tried to add different low pass filter at the AIN pins, the lowest cross frequency is around 8kHz, but the low pass filter has no use. This the reason why we think maybe there is frequency aliasing between internal master clock and external 2MHz noise. The aliased frequency is too low to be filtered by 8kHz LPF.

    I also want to know the function of internal master clock, whether it is the ADC's sample frequency or not?

    Tks.

    George

  • Hi Jellenie

    I want to know whether the internal master frequecny will be tested on final ATE or not? As for the samples that used to do  1000h HTOL or aging experiment, do you have test that batch of sample's master clock frequency at T0 and T1000h? If you do, could you please help to share the data?

    Tks.

    George

  • 0
    •  Analog Employees 
    on Jul 29, 2021 10:36 AM in reply to George_017

    Hi George, 

    The internal clock is divided by a factor of 2 to give 1MHz modulator frequency of the ADC.  

    You are requesting data that we do not usually provide so I was thinking that it might be good if we can take and discuss this offline. Have you tried to contact your local FAE? The product owner is currently on an annual leave. So I think I cannot provide you any definite answer regarding your requested data until next week. 

    In terms of how you measure the noise performance, have you just tried shorted the VINs and/or just bias it at midscale for example?

    Thanks,

    Jellenie

Reply
  • 0
    •  Analog Employees 
    on Jul 29, 2021 10:36 AM in reply to George_017

    Hi George, 

    The internal clock is divided by a factor of 2 to give 1MHz modulator frequency of the ADC.  

    You are requesting data that we do not usually provide so I was thinking that it might be good if we can take and discuss this offline. Have you tried to contact your local FAE? The product owner is currently on an annual leave. So I think I cannot provide you any definite answer regarding your requested data until next week. 

    In terms of how you measure the noise performance, have you just tried shorted the VINs and/or just bias it at midscale for example?

    Thanks,

    Jellenie

Children
  • Hi Jellenie

    Do you get the histogram of the master clock freuqency? Do yo have some other update?

    Please find our application as below, we tried to change the 200~349Ω resistor to 0Ω, but the ADC sampling resluts was still abnormal.

    Tks.

    George

  • 0
    •  Analog Employees 
    on Aug 5, 2021 3:21 AM in reply to George_017

    Hi, George. 

    I have asked histogram for one specific production lot, once I confirmed that it is okay to send then I'll send you through your personal email. or can you contact your local FAE? I just noticed that you are not using your company's email.

    However, I can't find HTOL data for this specific part. It seems that it was based from an AD7175 generic which uses different internal clock divider. 

    What's the pk-pk noise in time domain? Can you also send us a frequency response plot? I'd like to see where the signal is aliased? 

    I was wondering if adjusting the notch of the digital filter can help. I'm not sure if I asked this already do you have specific target ODR? or are you just operating at DC? What's your input bandwidth? 

    Thanks,

    Jellenie

  • Hi Jellenle

    Thanks for your replying. As our company might be mass market level, so I never contact a local FAE. You can send the histogram through my personal email.

    It is difficult to get the frequency response plot. We can only get some other parameters in system to assess the effect of interfering signal's frequency. As per the graph below, when the interfering frequency is closer to 2MHz, our system is more unstable. We've tried adjusted the notch of digital filter as low as 100Hz,the problem can be optimized but not solved. As we use ADC output data as input parameter of our system close loop control, so the ODR shouldn't be lower than 1ksps. As for the target frequency, the sampled sigal is related to operating temperature, so the frequency is almost DC. 

    Tks.

    George

  • +1
    •  Analog Employees 
    on Aug 12, 2021 3:07 AM in reply to George_017

    Hi George, 

    We'll try to closed this request offline. I'll send you an email within today. 

    Thanks,

    Jellenie

  • Hi JellenieR

    Sorry to reply you so late. I've got your data through email. Thanks a lot for your information.