AD2S1210 Excitation Gain and Faults

Hello,

I have been using AD2S1210 evaluation board with TI F28379D launchpad and control card. The default Excitation gains are 1.54 and 0.866 on 7.2 V peak to peak signal provided by the chip. I changed the gain to 2.74 by soldering 27.4 kOhm resistor at R10, R19, R30 and R39 and I can get 7Vrms as the excitation signal. My resolver has a transformer ratio of 0.5. So to reduce the amplitude of sine and cosine outputs I created a voltage divider using R22, R24 (Cosine) and R21, R26 (Sine). I used 28.7 kOhms for R22,R21 and 71.5 kOhms for R24,R26. The sine and cosine voltages are reduced to about 3V peak to peak from 3.5Vrms. 

I still see Sin/Cos clipping faults while using it with the EVAL-SDP-CB1Z. Can you please help me understand, what causes this fault and how can I mitigate it?

Regards,

Nakul Shah

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  • 0
    •  Analog Employees 
    •  Super User 
    on Jul 22, 2021 11:53 AM

    Nakul,

    If you are seeing clipping faults then one or more of your inputs is crossing one of the following thresholds (>AVDD-0.2V) or (< 0.15V) for a period greater than 4us. This most often occurs when the peak input signal magnitude for any single input is larger than the ~1.25V input common mode voltage causing the signal to clip the lower threshold.  

    When you say you have reduced the inputs to 3V pk-pk do you mean differentially or on each input leg.  If the latter you will need to further reduce the input magnitude to avoid the clipping faults.

    Sean

  •  Thank you Sean.

    I created a voltage divider using R22, R24 on cosine and R21,R26 on sine. The R23 and R25 are still o ohm resistors. In this case, should I decrease the voltage further?

    -Nakul

  • 0
    •  Analog Employees 
    •  Super User 
    on Jul 22, 2021 3:05 PM in reply to nakuk_shah

    Nakul,

    First of all you should make sure your divider is differential/symmetric with respect to the input to ensure you don't add any unintended mismatches to the input.    

    Secondly I think your attenuator does need to be a bit more aggressive as (if I've done my math correctly) I think you are seeing about 3 to 3.5Vpp on each input or (6 to 7Vpp differential) which is outside the range of the device.  Some quick calculations looks like we want closer to 50K (52.7K) in each of R23-R26 to attenuate the nearly 10V pp differential at the input down to 4Vpp differential.  Again I based this on the 3.5VRMS is the output of your secondary (max).

    Hope that helps.

    Sean

  • Sean, 

    3.5 Vrms is differential voltage across sin/cos and sinlo/coslo. So the device should see 3.5*1.4142*2*28.7/(28.7+71.5) = 2.84 V (Peak to Peak). Does this makes sense?

    I will work on creating the divider symmetric to check if that's what causing the problem.

    -Nakul

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