Products Mentioned

LTC2325-12 Production
The LTC2325-12 is a low noise, high speed quad 12-bit + sign successive approximation register (SAR) ADC with differential inputs and wide input common...
Datasheet
LTC2325-12 on Analog.com

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LTC2325 timing diagram question

		
	
				

			

									
					    JackChan
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jul 16, 2021 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
		    			
    
			    
    1. LTC2325-12 first 3 bit show 000,means it goes low or another?
    

    test sample and evb
    

      
    

    2. double check the LTC2325 series datasheet, the page 15/16, page 26/27 Seems to be out of tune
    

     
    

       
    

       
    

        
    

    

    best regards
    

    jack.C
    

    
			
    
			
									
		                             
                        

    
    
                                            
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							FormerMember
					
      
		
      
		    
		    		    
			
				
									FormerMember
							        
			
			
			
    
            
						
                            
            
            				
            
                on Jul 23, 2021 3:20 AM
            
            
						
			            		
    
		
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    Hi Jack,
    

    I moved your thread to Precision ADC community. Someone here might be able to assist your concern.
    

    Regards,
    

    Meriam
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    


	

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    •  Analog Employees  
    •  Super User  
    
            
						
                            
            
            				
            
                on Jul 23, 2021 3:50 AM
            
            
						
			            		
    
		
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    Hi,
    

    We'll contact the product owner and get back to you.
    

    Regards,
    

    Andrei
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Jul 23, 2021 9:39 AM
            
            
						
			            		
    
		
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    Hi Jack,
    

    The timing diagrams showing tconv before shifting out the data are in error. The data sheet is in the process of being corrected.
    

    16 sck edges are required for proper operation in SDR mode. Data after B0 can be ignored.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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