wanted to ask a question about on-chip conversion clock in AD7091R-4

you are not defining on-chip conversion clock in AD7091R-4 datasheet, what is it's significance in this AD chip? and is it generated from pll? and is CONVST signal regular and coming after each micro second?

Parents
  • 0
    •  Analog Employees 
    on Jun 30, 2021 8:26 AM

    Hi Sumbal-Maham,

           The on-chip conversion clock is internal to the AD7091R-4. This clock operates during the conversion cycle of the AD7091R-4.  The On-Chip conversion clock is independent of the SCLK. SCLK is used in the communication interface to read and write to the AD7091R-4.

         The CONVST pin accepts the signal to initiate an ADC conversion. A minimum of 10ns is required for the CONVST to go low to initiate a proper conversion. This signal is driven externally from a digital source like microcontroller, DSP or FPGA. When the conversion time has elapsed after conversion was initiated, CS then can go low to frame and read the conversion data.

    Regards,

    Jonathan

Reply
  • 0
    •  Analog Employees 
    on Jun 30, 2021 8:26 AM

    Hi Sumbal-Maham,

           The on-chip conversion clock is internal to the AD7091R-4. This clock operates during the conversion cycle of the AD7091R-4.  The On-Chip conversion clock is independent of the SCLK. SCLK is used in the communication interface to read and write to the AD7091R-4.

         The CONVST pin accepts the signal to initiate an ADC conversion. A minimum of 10ns is required for the CONVST to go low to initiate a proper conversion. This signal is driven externally from a digital source like microcontroller, DSP or FPGA. When the conversion time has elapsed after conversion was initiated, CS then can go low to frame and read the conversion data.

    Regards,

    Jonathan

Children