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AD7705 Why My dataOut is empty ?

Hello, i'm new with the AD7705 and when i lanch my program, i only see the when CS goes low...

i'm using a pic16f18344 (master) with a ad7705 (slave) in SPI communication

And here is my code : 

#define _XTAL_FREQ 16000000
// CONFIG1
#pragma config FEXTOSC = OFF // FEXTOSC External Oscillator mode Selection bits (Oscillator not enabled)
#pragma config RSTOSC = HFINT1 // Power-up default value for COSC bits (HFINTOSC (1MHz))
#pragma config CLKOUTEN = OFF // Clock Out Enable bit (CLKOUT function is disabled; I/O or oscillator function on OSC2)
#pragma config CSWEN = ON // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor is disabled)

// CONFIG2
#pragma config MCLRE = ON // Master Clear Enable bit (MCLR/VPP pin function is MCLR; Weak pull-up enabled)
#pragma config PWRTE = ON // Power-up Timer Enable bit (PWRT enabled)
#pragma config WDTE = OFF // Watchdog Timer Enable bits (WDT disabled; SWDTEN is ignored)
#pragma config LPBOREN = OFF // Low-power BOR enable bit (ULPBOR disabled)
#pragma config BOREN = ON // Brown-out Reset Enable bits (Brown-out Reset enabled, SBOREN bit ignored)
#pragma config BORV = HIGH // Brown-out Reset Voltage selection bit (Brown-out voltage (Vbor) set to 2.7V)
#pragma config PPS1WAY = OFF // PPSLOCK bit One-Way Set Enable bit (The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence))
#pragma config STVREN = OFF // Stack Overflow/Underflow Reset Enable bit (Stack Overflow or Underflow will not cause a Reset)
#pragma config DEBUG = ON // Debugger enable bit (Background debugger enabled)

// CONFIG3
#pragma config WRT = OFF // User NVM self-write protection bits (Write protection off)
#pragma config LVP = OFF // Low Voltage Programming Enable bit (High Voltage on MCLR/VPP must be used for programming.)

// CONFIG4
#pragma config CP = OFF // User NVM Program Memory Code Protection bit (User NVM code protection disabled)
#pragma config CPD = OFF // Data NVM Memory Code Protection bit (Data NVM code protection disabled)

#include <xc.h>
#include <pic16f18344.h>
#include <stdint.h>

/////////// CAN ////////////
#include <math.h>
#define SCK RC0 //Serial Clock
#define SDI RC1 //Serial Data In
#define SD0 RC2 //Serial Data Out
#define SS RC3 //Slave Select: Not used in this application
#define DRDY RB6
#define RESET RB5
#define NUM_SAMPLES 1000 /* change the number of data samples */
#define MAX_REG_LENGTH 2 /* this says that the max length of a register is 2 bytes */

//modes de configs
#define ADC_NORMAL 0x00
#define ADC_SELF 0x40
#define ADC_ZERO_SCALE 0x80
#define ADC_FULL_SCALE 0xc0

//Réglages de gain
#define ADC_GAIN_1 0x00
#define ADC_GAIN_2 0x08
#define ADC_GAIN_4 0x10
#define ADC_GAIN_8 0x18
#define ADC_GAIN_16 0x20
#define ADC_GAIN_32 0x28
#define ADC_GAIN_64 0x30
#define ADC_GAIN_128 0x38

//Unipolaire ou Bipolaire
#define ADC_BIPOLAR 0x04
#define ADC_UNIPOLAR 0x00

//Fréquence d'envoi
#define ADC_50 0x04
#define ADC_60 0x05
#define ADC_250 0x06
#define ADC_500 0x07


uint8_t prems;
uint8_t deus;


void Init_Horloge(void){
//// HORLOGE ////
OSCCON1 = 96;//96+?

OSCEN=64;
OSCFRQ = 6;
}

void CAN_Init(void)
{

SSPBUF = 0; // init buffeur spi
SS = 1; // Slave select init

//// PORTS SPI SENS ////
TRISC3 = 0; // Slave select en sortie
TRISC0 = 0; // SCK en sortie
TRISC1 = 1; // SDI en entrée
TRISC2 = 0; // SDO en sortie
TRISB6 = 1; // DRDY CAN en entrée
TRISB5 = 0; // RESET Sortie

//// SPI PPS ////
RC0PPS= 24; //Affectation sck
RC2PPS = 25; //Affectation sdo

//// SPI CONFIG ////
SSP1STAT = 128; // mesure millieu safe
SSP1CON1 = 34; //SPI enable + Mode maitre
SSP1CON3 = 16; //Autorisation overwrite


ADCON0 = 0 ; // Désactivation du CAN
ANSELA = 0;
ANSELC = 0;
ANSELB = 128;


}

//////////////////////// ECRITURE CAN /////////////////////

void write_adc_byte(uint8_t data)
{

SS = 0; // Activation Slave select
//RB7 = 0 ;

SSP1BUF = data;//envoi dans buffer
while(!SSP1IF){}
SSP1IF = 0; // doit être remis à 0 manuellement



//RB7 = 1;
SS = 1;// désactivation Slave select

}

//////////////////////// LECTURE CAN /////////////////////
uint8_t read_adc_word()
{
uint8_t data2_msb;
uint8_t data2_lsb;

while(DRDY ==1){}
SS = 0;

SSP1BUF = 0;
while(!SSP1IF){}
SSP1IF = 0;
data2_lsb= SSP1BUF; //envoi dans buffer



SSP1BUF = 0;
while(!SSP1IF){}
SSP1IF = 0;
data2_msb= SSP1BUF; //envoi dans buffer
SS = 1;

//while ( DRDY == 0 ){};

return data2_lsb;
}

//Configurations
void setup_adc_device(int calmode, int gainsetting, int operation, int rate)
{
write_adc_byte( 32 );//Registre de communications réglé pour écrire dans le registre d'horloge
write_adc_byte( 12 );//Registre d'horloge
write_adc_byte( 16 );//Registre de communications réglé pour écrire dans le registre de setup
write_adc_byte( 64 );//Registre de setup
}

//initailaization routine

void adc_init()
{
RESET = 0;//Etat bas reset
RESET = 1; //Etat haut reset
//setup_adc_device(ADC_SELF,ADC_GAIN_1,ADC_BIPOLAR,ADC_50); // Lancement config

}

void adc_disable()
{
write_adc_byte( 0x20 );
write_adc_byte( 0x10 );
}

//Convertir la valeur lue en volts
float convert_to_volts(long data){
return ((float)data*2.5/0xffff);
}



void main(void) {


Init_Horloge();
CAN_Init();

RB7 = 0;


adc_init();

write_adc_byte( 32 );//Registre de communications réglé pour écrire dans le registre d'horloge
write_adc_byte( 7 );//Registre d'horloge
write_adc_byte( 16 );//Registre de communications réglé pour écrire dans le registre de setup
write_adc_byte( 64 );//Registre de setup (+56 pour gain max)

while(DRDY ==1){}

while(1){

write_adc_byte(56);
//__delay_ms(10);
prems= read_adc_word();
UART_Write(32);

}





return;
}

My sending spi is good but i don' see any data into my dataout pin

PLS help

Parents
  • Hi, 

    I am sorry I am not a coder. Can you send me a summarize register map settings? And I would recommend to try to readback other register settings to know if your SPI communication is working correctly. 

    Can you share your schematic/setup as well? Please probe and provide details on MCLK, supplies, reference voltage and input voltage.

    Another worth trying is upon power up, just pull /CS low and monitor the DRDY pin if it is pulsing at default ODR. Then try to change the ODR by writing to clock register, again monitor the DRDY pin with /CS low and see if it is now pulsing at the new selected ODR. 

    May I know also if this is for a new design? This is an old part and I would recommend to use our new products such as AD7124 which has all the building blocks plus more advanced features. 

    Thanks,

    Jellenie

  • He here is my setup for testing the AD7705 : 

    And if i let the CS pin low, DRDY don't pulse at default but if i use CS for sending commands DRDY can pulse normally

  • Hi, 

    Looks like the DRDY pin is separate from the DOUT pin so I think even without tying /CS low the DRDY pin should still be pulsing at correct ODR. If it is not pulsing then the ADC seems not converting.

    Can you probe your MCLK and VREF please? To ensure that you have valid inputs for both of these.

    And just to confirm, can you share a scope shot when you probe DRDY, please take note that I think the default ODR is 60SPS. So you should consider that in the scope settings. And also when monitoring DRDY pin please disconnect the SPI interface and Reset pin. If you can just pull high the reset pin and pull /CS low then that would be great. This is just to check if the DRDY pin goes low to indicate the end of conversion.

    And in terms of reading back the other register settings, did you try reading it back? This is just to confirm that the device is communicating with the MCU.  

    And also can you share the register map settings? So we can understand how the ADC is configured. 

    Thanks,

    Jellenie

  • Sorry what is 0DR please ?

    Here is my MLCK (2.4MHz) on the top with My Vref under (2.57 V) :

    And here is my DRDY when i have send the 4 registers :

    60 SPS is like 60 Hz ?

    And on which pin i am supposed to read back the registers please ?

    Here is my configuration : 

    write_adc_byte( 32 );// or 0x20 in hexadecimal
    write_adc_byte( 12 );// or 0x0C in hexadecimal
    write_adc_byte( 16 );// or 0x10 in hexadecimal
    write_adc_byte( 64 );// or 0x40 in hexadecimal

    i have take the same configuration as the datasheet 

    Thank you

  • Hi, 

    So the DRDY seems pulsing at correct ODR (output data rate). Yes 60SPS could also mean 60Hz. In your code you should be monitoring that DRDY pin, when it goes low that's the time you will write 0x38 and supply the 16 SCLKs for data. 

    To readback the other register you just need to write to comm register somehow like the 0x38 instruction but the RS2-RS0 bits will be different. This is just to confirm if your SPI communication interface is working correctly. The interface is SPI so the data read rom the ADC will always come from the DOUT pin and the data write to the ADC should be in DIN. I am not sure if that is what you are asking.

    So for example try to read the setup register. Instead of writing 0x38 you should now write 0x18 and supply 8 SCLKs for setup register content. 

    I am not sure if I understand your configuration shown here. Can you explain this please? I was asking for registers configuration.

    Here is my configuration : 

    write_adc_byte( 32 );// or 0x20 in hexadecimal
    write_adc_byte( 12 );// or 0x0C in hexadecimal
    write_adc_byte( 16 );// or 0x10 in hexadecimal
    write_adc_byte( 64 );// or 0x40 in hexadecimal

    For example the default config for Setup register is 0x01. So you should read back the same. Please take note that the interface works by counting clocks so if you are writing 12 bits to an 8bits register for example will cause some issue. So you need to ensure that correct number of SCLKs is provided when writing or reading to a certain register. 

    Thanks,

    Jellenie

  • Ok i see

    Ah i misunderstood yes i can see what i send ; here is my configuration : 

    i can see them

    I send 0x18 instead of 0x38 : 

    And for my configuration : 

    write_adc_byte( 32 ); means RS1 = 1 and others = 0 in communication register
    write_adc_byte(  7  ); means CLK , FS1 and FS0 = 1 , and others = 0 in clock register
    write_adc_byte( 16 ); means RS0 = 1 and others = 0 in communication register
    write_adc_byte( 64 ); means MD0 = 1 and others = 0 in setup register

    But i noticed that i shouldn't be able to have 60 SPS because i put CLK , FS1 and FS0 at 1 ; With this configuration i should be at 500 SPS 

    Because i have a clock with 2,4 MHz no ?

    I've just stated that even if i change the clock register, i'm always at 60 SPS 

  • Hi, 

    Did you try to read back the clock register after changing its value? In that way you will confirm that you have successfully write to register. 

    For example after writing 0x18, you need to supply another 8SCLKs for the 8 bit setup register data. What's the value that you have read? 

    If the ODR is not updating, there's a chance that  you are not successfully writing to the ADC, as it always run at default register settings. 

    Thanks,

    Jellenie

  • Hi 

    By reading back the register, you mean reading what i've send on the oscilloscope ?

    If yes i can see this like that : 

    And now i can change my SPS, that's because i've set CKE = 0 and CKP = 0 instead of CKE = 0 and CKP = 1

    Now i can change the rate as i want !

    50 Hz : 

    60 Hz : 

    250 Hz : 

    500 Hz : 

    Thank you

  • Hi, 

    No, what I was asking is what's the data in DOUT not DIN. So for example after writing 0x18, and then supply 8 SCLKs what do you see on DOUT line. Just to avoid confusion I think we can said that if I mentioned write then the data is at DIN line but if I mentioned read then the data that I was asking is at DOUT line. :)

    But good to see that you are progressing. However, it is still confusing as you are using different terms. But I guess CKE means CLKDIV and CKP means CLK? Is that correct? 

    Either way I believe that the ODR should be updated. The important thing there is that CLKDIV is 0 since you are using a 2.4576MHz clock. 

    Thanks,

    Jellenie

  • Hi !

    Ah yes when said CKP (Clock Polarity Select bit otherwise called CPOL) and CKE (Clock Edge Select bit otherwise called !CPHA ) it's the way how i sending my register in SPI (in my PIC16F18344)

    and when my CKP was at 0 instead of 1, that means my writing message begin at 0 instead at 1 

      that was causing some misunderstanding

    it has different ways to send a byte in SPI but now i understand my mistake 

    Ok so when i'm sending 0x28, my DOUT recieve this : 

    I'ts good because i have put 0x04 in my clock register (CLK = 1 for 50 Hz)

    and i'm sending 0x18, my DOUT recieve this : 

    I'ts rather good because i have put 0x01 but the signal doesn't go low right after no ?

    Thank you very much

    Thomas

  • HI, 

    Looks like I misunderstood that again. So you are referring to SPI interface mode and not the ADC clock mode. hehe.. 

    Anyways, I believe the interface operates in SPI Mode 3 (CPOL=1, CPHA=1) wherein SCLK idles high, the falling edge of SCLK is the drive edge, and the rising edge of SCLK is the sample edge. Data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. So I guess you still need to update your SPI config. 

    Thanks,

    Jellenie

Reply
  • HI, 

    Looks like I misunderstood that again. So you are referring to SPI interface mode and not the ADC clock mode. hehe.. 

    Anyways, I believe the interface operates in SPI Mode 3 (CPOL=1, CPHA=1) wherein SCLK idles high, the falling edge of SCLK is the drive edge, and the rising edge of SCLK is the sample edge. Data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. So I guess you still need to update your SPI config. 

    Thanks,

    Jellenie

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