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AD7386 SPI Configuration

I am trying to talk to an AD7386 from an STM32, and trying to do a simple readback of the register bank at power-up. I have some queries about the command protocol, that I am hoping to clarify here.

1. The AD7386 has 3v3 on Vcc and Vlogic.
2. The STM32 is the SPI bus Master. We have seen it drive nCS low, under firmware control. We see data on SCLK, and on SDI, when nCS is low. We also see data on SDOA, too, but not the register readback returns expected.

I expect Registers 1 - 4 to be 0, at power-up, and Register 5 to be 0x0FFF.

I think the datasheet suggests that SCKL should be CPOL = 1 & CPHA = 1, too, but I see AD7386 noOS software driver defines it as CPOL = 0 & CPHA = 1. I've also seen an Engineering Zone forum post say that's CPOL = 1 & CPHA = 0.

I am using a command protocol of :

1. Drive Chip-select Low.
2. Perform an SPI Write-then-Read command to transmit the Register Access Command.
3. Toggle Chip-Select High/Low.
4. Perform a second SPI Write-then-Read command to transmit a NOP, and read the Register contents.
5. Drive Chip-select High.

I am transmitting commands as MSB first, with Bit 15 set as the Read/Write access bit, Bits 14-12 as the Register address, and Bits 11-0 as the register data.

So, 3 questions, please :

1. What is the recommended Clock Phase & Polarity?
2. Is AD7386 MSB first?
3. Should I toggle chip-select between the write command & NOP/read return command?

All advice appreciated.

Regards

John

  • Hi John, 

    We’ve notified the product owner regarding this concern. Please wait for him to comeback and address this issue. 

    Thanks,

    Jellenie

  • Hi John,

           On the AD738x, The data is clocked out on the rising edge of the SCLK. This should have a CPOL=1 and CPHA=0. The AD7386 device outputs MSB first with straight binary coding. When reading and writing to the AD7386, the CS must go low. When reading the register, a command of 0 + [reg address ] must be sent to the SDI line. On the next CS high to low transition, the register data is clocked out on the SDOA pin. When writing, please follow the setup time (Tsdis) and hold time (Tsdih) requirement to correctly write to the device.

    Regards,

    Jonathan