LTC2387-18
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The LTC2387-18 is a low noise, high speed, 18-bit 15Msps successive approximation register (SAR) ADC ideally suited for a wide range of applications. The...
Datasheet
LTC2387-18 on Analog.com
Hi,
What is the intended procedure of resetting the ADC data bus? How do we make sure that the shift register used to clock out the data is reset to its initial value?
Does it happen somewhere during input acquisition? Or do I need to shift the test pattern to properly initialise the chip?
Thank you,
Anton
Hi Anton,
We will coordinate this to the product apps so he can better assist you.
Thanks,
Jellenie
After power powering up or exiting power-down, the next two conversions produce invalid data. Subsequent conversions will produce valid data as long as the time between conversions meets the tcyc specification. There is no procedure necessary to reset the shift register.