AD7606C-16: The relationship between SCLK frequency and sampling rate

Hi ttd,

The sample rate comes dictated by the CNVST signal frequency. However, you need to clock out the data in between two CNVST pulses.

So, if your SCLK is 16 MHz, but you need to clock out 8ch*16bits=128 clocks, that means you max sampling frequency is 125kSPS.

But if you have four channels in ADCa and four channels in ADCb plus you can handle two MISO lines(DOUTa and DOUTb), you can run duplicate that speed. Another alternative is to use the parallel interface for faster throughputs.

Regards,

Lluis.

Hey , can anyone explain how we achieved a max sampling frequency of 125kSPS

Hi Jateen,

By applying a 125 kHz signal in CNVST pin and using SCLK frequency faster than the below, for each case:

Hi Jateen,

By applying a 125 kHz signal in CNVST pin and using SCLK frequency faster than the below, for each case:

Thank you for the response

Is this a general case or dependent on the ADC we use

Hi Lluis,

We are trying to use an ADC ( ADS124S08) to read data from a set of batteries, we are using a 5 volt external reference for the ADC using SPI.

While reading the output it is all 1s , irrespective of the battery we connect ( even when we disconnect the battery).

We did try resetting the ADC

Could you please look into this and help us.

Hi Jateen,

ADS124S08 is not an Analog Devices' product, so we cannot support you on this question I'm afraid. 

Regards,

Lluis.