AD7606C-16: The relationship between SCLK frequency and sampling rate

Dear Technical Support Team,

Is there relationship between SCLK frequency and sampling rate?

According to the datasheet, 60MHz(VDRIVE > 2.7 V) is the max frequency.

My microcontroller is max 16MHz for SCLK. 

My target is over 200ksps and 8ch simultaneous sampling. SPI is serial interface.

Best Regards,

ttd



Add "SPI I/F is serial mode."
[edited by: ttd at 11:10 PM (GMT -4) on 25 May 2021]
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  • +1
    •  Analog Employees 
    on May 26, 2021 6:10 AM

    Hi ttd,

    The sample rate comes dictated by the CNVST signal frequency. However, you need to clock out the data in between two CNVST pulses.

    So, if your SCLK is 16 MHz, but you need to clock out 8ch*16bits=128 clocks, that means you max sampling frequency is 125kSPS.

    But if you have four channels in ADCa and four channels in ADCb plus you can handle two MISO lines(DOUTa and DOUTb), you can run duplicate that speed. Another alternative is to use the parallel interface for faster throughputs.

    Regards,

    Lluis.

Reply
  • +1
    •  Analog Employees 
    on May 26, 2021 6:10 AM

    Hi ttd,

    The sample rate comes dictated by the CNVST signal frequency. However, you need to clock out the data in between two CNVST pulses.

    So, if your SCLK is 16 MHz, but you need to clock out 8ch*16bits=128 clocks, that means you max sampling frequency is 125kSPS.

    But if you have four channels in ADCa and four channels in ADCb plus you can handle two MISO lines(DOUTa and DOUTb), you can run duplicate that speed. Another alternative is to use the parallel interface for faster throughputs.

    Regards,

    Lluis.

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