I might be confused (again) but shouldn't the bias voltage applied to the resistive dividers be labeled as REF+ and not AVDD? As shown, wouldn't the offset voltage be sensitive to changes on the AVDD voltage?
No. The figure is correct. But I guess the error will depend on how stable your supply. The datasheet provide the PSR and from there then you can calculate the expected error introduce by errors in your supply. But I guess in a typical application with proper power supply circuit and isolation this should not introduce large errors.