AD7124 Differential input current

I have a question about the differential input current for the AD7124-8

The AD7124-8 data sheet states "diferential input current +/-1.5nA (typ)" for the full power mode.

Other similar ADC's available in the market publish the differential input current vs input voltage. For example (Below)

Is this true for the AD7124-8, does the differential input current vary with differential input voltage for the buffered mode or is it a fixed value for any input voltage ?

What are the test conditions for the AD7124-8 below, is this with 0V input for example ?

Regards,

Adrian.

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  • 0
    •  Analog Employees 
    on May 14, 2021 2:26 AM

    Hi, 

    I believe the actual VINs varies with selected Gain which is color coded but the typical average input current is quite similar or close in buffered mode and at all gains. There will also a slight difference in terms of power mode. But in general It is expected that in buffered mode the average input current is very small compared to unbuffered mode because of its very high input impedance. Thus, any change in input voltage has no significant effect.

    In terms of the test conditions, I am not sure about the actual number but I assumed this should be close to ±VREF/gain. Let me confirm this. May I know your application and how critical this spec to you? 

    Thanks,

    Jellenie 

  • Hi,

    I have a very small differential voltage to measure accurately, it's a differential signal sitting on top of the main differential input measurement, it is only 40uV, so the differential leakage current becomes a large amount of the measurment. Also I cannot calibrate this offset out because of the input set up.

    Main I/P = 30mV, compensation signal = 40uV sitting on top of 30mV I/P.

    The differential leakage mismatch is +/-1.5nA (Typ) in high power mode, and I have two 3K1 resistors for the differential input pair to limit the fault current to10mA with +/-30V miss wired to the input.

     Error= 1.5nA *3K1*2 = 9.3uV.

    + 25pA/C drift as well

    I have investigated the use of a chopping technique to remove the offset. This appears to resolve the offset to the level of measurement noise, as described in one of your app notes. This means taking two samples one of them with reversed Mux polarity and averaging sample pairs to remove the offset, I have simulated it and it works well.

    www.analog.com/.../AN-609.pdf

Reply
  • Hi,

    I have a very small differential voltage to measure accurately, it's a differential signal sitting on top of the main differential input measurement, it is only 40uV, so the differential leakage current becomes a large amount of the measurment. Also I cannot calibrate this offset out because of the input set up.

    Main I/P = 30mV, compensation signal = 40uV sitting on top of 30mV I/P.

    The differential leakage mismatch is +/-1.5nA (Typ) in high power mode, and I have two 3K1 resistors for the differential input pair to limit the fault current to10mA with +/-30V miss wired to the input.

     Error= 1.5nA *3K1*2 = 9.3uV.

    + 25pA/C drift as well

    I have investigated the use of a chopping technique to remove the offset. This appears to resolve the offset to the level of measurement noise, as described in one of your app notes. This means taking two samples one of them with reversed Mux polarity and averaging sample pairs to remove the offset, I have simulated it and it works well.

    www.analog.com/.../AN-609.pdf

Children
  • +1
    •  Analog Employees 
    on May 14, 2021 10:54 AM in reply to AdrianK

    Hi, 

    Thanks for this info. Good to hear that the chopping will resolve your issue. Just take note that since chopping uses two consecutive conversions it has a drawback in terms of the actual throughput. But hopefully this will still able to meet your target speed as the ADC offers flexible filter options and ODR. 

    Thanks,

    Jellenie