AD7386 in One Wire mode

Hi Steve,

       I can see that you have two sets of 16 SCLK cycles and I assume this is to read SDOA and SDOB. how much is the gap between these two sets? Would you be able to adjust the SCLK cycle? Like a continuous 32 SCLK cycles to read both conversion results of ADCA anf ADCB in SDOA. 

Regards,

Jonathan 

HI Jcolao, thanks for the reply.

It is not possible to have a continuous train of 32 clocks with the dsPic33FJ series using the SPI port. 16 bits data size is the most you can select.

I have tried the two groups of 16 clocks separated by a couple of microseconds but this did not work either.

What is the maximum delay one can have between two groups? I thought it might be a static shift register design.

I am keeping the CS low all of the cycle so I would have thought that the chip would be waiting for more clocks.

Most microprocessors limit you to 16 bit transfers.

I can try shortening the delay between pulse trains to around 500ns if you think this will help.

Regards

Steve

Hi Steve,

     In the CS signal, I see that there is a consecutive high to low transition. How long was the 1st low transition? Does it equal conversion time? I am asking this because the AD7386 when CS goes low, starts conversion and must stay low which is equal to conversion time to complete the conversion process. And since the conversion result is one cycle latency, the conversion result can be read in the next CS high to low transition. 

Regards,

Jonathan

Hi Steve,

     In the CS signal, I see that there is a consecutive high to low transition. How long was the 1st low transition? Does it equal conversion time? I am asking this because the AD7386 when CS goes low, starts conversion and must stay low which is equal to conversion time to complete the conversion process. And since the conversion result is one cycle latency, the conversion result can be read in the next CS high to low transition. 

Regards,

Jonathan

Hi Jcolao,

the inital Conversion pulse is around 5 uS. The datasheet says the AD7386 conversion time is 190nS so this should be plenty, The A channel is converting correctly but the B channel does not appear on the SPI output on SDOA in One Wire Mode.

Incidently, I have added a multiplexer to the output of SDOA and SDOB in Two Wire Mode and it converts correctly using two 16-bit SPI cycles.

We would really prefer to use the device in ONE Wire Mode if possible though. What is the maximum delay that is allowed between two groups of 16 SCLK's in One Wire Mode?

Thanks

Steve

Hi Steve,

         After writing to the AD7386 registers to use the 1-wire mode. Was there data coming out in the SDOB pin? This should confirm that the write to register was successful. I did some experiments and found that it is working fine, this is how my timing diagram looks like when writing to the AD7386. 

This is how the digital signal looks before the register write. Both SDOA and SDOB has conversion data output.

This is how the data looks after the write. all conversion output is seen only at SDOA. The timing on the DIN for configuration register 2 bit 8  allows having a 1- wire mode. The data written is 0xA100.

Regards,

Jonathan

Thanks for your perseverance Jonathan.

Firstly, you seem to be outputting 33 SCLK's. Is it just that the last clock is ignored.

Next, you seem to be writing 0xA100 to register 2 in the same CS cycle that you are reading the data. The datasheet implies that one should write the register in one CS cycle and then read the data on the next. Is this correct?

It is not possible for us to output 32 consecutive SCLK's so we have to do two 16 bit reads with a gap in between (within the same CS cycle)

Also, there is some concern that the Pad terminal underneath the chip may not be connected. Would this affect the digital communication or just the analog screening?

Best regards

Steve

Hi Steve,

     The last SCLK cycle can be ignored. In that picture that short pattern runs repeatedly. It was a quick pattern verification to quickly confirm the write to the register for the 1 wire mode. I think the gap between two sets of 16SCLK cycles is OK. I also tried running this pattern with a wide gap between two sets of 16 SCLK cycles. I don't think the pad will affect.

      Just curious, have you check when no data output on the SDOA for channel, does it have data out[ut in the SDOB pin?

Regards,

Jonathan

Sorry Jonathan,

my last reply did not seem to get through.

When programmed into 1-wire mode, which was confirmed by reading back the configuration register, the device still output data on SDOB.

We have decided to go with my multiplexer fix, which is very simple and takes hardly any PCB real estate. It also removes the need for the 100 ohm ourput resistor.

This gives us the opertunity to revert to 1-wire mode if we ever get it to work in the future.

Many thanks for your help. I hope that I am the only person to have this problem but if anyone else is stuck I can forward my multiplexer schematic.

Best regards

Steve