Hi, I'm working on a project using AD4110-1.
There are some things that I don't know using this chip.
I know that
1. SYNC Logic 'Low' means it will abort all ADC Operations
2. SYNC Logic 'High' means it will start new conversion within a number of clock cycles.
3. CS is brought low and data is available to read when RDY goes low.
so, I set my ADC register like below (I did also set other registers)
a. ADC_MODE Register(0x1) - 0x0008. (Reference Enable, No Conversion Delay, Continuous conversion mode, External clock from CLKIO pin)
b. ADC_INTERFACE Register(0x2) - 0x0400. (ADC Status Enable, CRC Disable, Conversion result is 24-bit long)
c. Filter Register(0x5) - 0x0E00. (Enable enhanced 50/60HZ filter, ODR = 16.67 SPS, settling time = 60 ms., Sinc5 + sinc1 , ODR : 125 kSPS)
d. ADC_GPIO_CONFIG Register(0x6) - 0x0800. (SYNC pin Enable)
As you look at the registers, conversion mode is Continuous conversion mode so I keep my SYNC Logic 'High'.
Q1. Can I keep sending SYNC signals high? (I think SYNC high signal is not the positive edge of clock, literally high)
Q2. ODR(125kSPS) means AD conversion data is generated every 8us? or 8us + a number of clock cycles(8Mhz = 125ns)?
Q3. If AD conversion data is generated every 8us(or 8us + a number of clock cycles) and right after CS is brought low, /RDY will go low?
Q4. (If I want to read AD Conversion data) before writing 8-bit Command(0x44), SCLK and DIN should keep high?? (I'm wondering that these signals are stretched by H/W or Users)
I could set register and check my register I set right before.
However, I can't get any AD conversion data at all.
Q5. Could you tell me what am I doing wrong? (SYNC is high)
- Why RDY isn't brought low?
I wish you could give me some ADC examples or images.
Thank you for replying.