AD4110-1 ADC issue

Hi, I'm working on a project using AD4110-1.

There are some things that I don't know using this chip.

I know that

1. SYNC Logic 'Low' means it will abort all ADC Operations

2. SYNC Logic 'High' means it will start new conversion within a number of clock cycles.

3. CS is brought low and data is available to read when RDY goes low.


so, I set my ADC register like below  (I did also set other registers)

a. ADC_MODE Register(0x1)                - 0x0008. (Reference Enable, No Conversion Delay, Continuous conversion mode, External clock from CLKIO pin)

b. ADC_INTERFACE Register(0x2)      - 0x0400. (ADC Status Enable, CRC Disable, Conversion result is 24-bit long)

c. Filter Register(0x5)                            - 0x0E00. (Enable enhanced 50/60HZ filter, ODR = 16.67 SPS, settling time = 60 ms., Sinc5 + sinc1 , ODR : 125 kSPS)

d. ADC_GPIO_CONFIG Register(0x6)  - 0x0800. (SYNC pin Enable)


As you look at the registers, conversion mode is Continuous conversion mode so I keep my SYNC Logic 'High'.

Q1. Can I keep sending SYNC signals high?  (I think SYNC high signal is not the positive edge of clock, literally high)

Q2. ODR(125kSPS) means AD conversion data is generated every 8us? or 8us + a number of clock cycles(8Mhz = 125ns)?

Q3. If AD conversion data is generated every 8us(or 8us + a number of clock cycles) and right after CS is brought low, /RDY will go low?

Q4. (If I want to read AD Conversion data) before writing 8-bit Command(0x44), SCLK and DIN should keep high??  (I'm wondering that these signals are stretched by H/W or Users)

I could set register and check my register I set right before. 

However, I can't get any AD conversion data at all. 

Q5. Could you tell me what am I doing wrong? (SYNC is high)
       - Why RDY isn't brought low?

I wish you could give me some ADC examples or images.

Thank you for replying.

  • +1
    •  Analog Employees 
    on May 4, 2021 7:11 AM

    Hi Park,

    1. SYNC needs to be HIGH all the time for the correct operation of the device. The part will RESET modulator/digital blocks whenever SYNC is low. Hence, there is approx. 65.5MCLKS added to the settling time for the first conversion whenever SYNC is used. Any conversions triggered by SYNC will add this delay.
    2. That’s correct. ODR 125ksps means data is generated every 8us, 125ns is not added. Only the first sample will have a settling time. This is true only if one channel is enabled. For more than one channel enabled, you can refer to Table 16-19 of the datasheet for switching rate.
    3. Yes, ADC converts data every 8us in this case. One has to pull /CS down and monitor /RDY to go low for data ready.
    4. DIN and SCLK should be HIGH before writing the 8-bit command.
    5. I would suggest you check the default settings first before moving forward. After power-up, pull /CS low and monitor the /RDY pin.

    Also, ADC_Interface register should be 0x0040 whereas you have mentioned 0x0400. Please correct if it is wrong in your code.

    You have configured the part to enhanced filter with 16.67sps. If you pull /CS high then you might miss out on the /RDY to go low. Please pull /CS low and monitor /RDY for data ready operation.



    Vikas J

  • Thanks for replying Vikas.

    While verifying based on your advices,  I have few more questions.

    Q1. Is MCLKS Internal ADC Clock (8Mhz =125ns) ? 

    Q2. You told me that DIN and SCLK should be HIGH before writing the 8-bit command, then when /CS is brought low, at the same time DIN and SCLK should be HIGH? or after one or some clocks, DIN and SCLK should be HIGH? I want to know the timing sequence between /CS and DIN and SCLK.

    Q3. You told me that 65.5MCLKS added to the settling time for the first conversion, Does it mean I should wait almost 16.25us (8.178us(=65.5MCLKS,  65.5 * 125ns) + 8us(ODR = 125ksps)) right after I bring SYNC LOW to HIGH?

    Q4. I set ODR as 125ksps so it will generate ADC conversion data every 8us, but I can't see /RDY is brought low when /CS is LOW(see the picture below). I didn't put any 8-bit command almost 17.4us after /CS is brought LOW. (SYNC is LOGIC HIGH and I have waited almost 17.4us because of first conversion so i have waited more than 16.25us) 

  • 0
    •  Analog Employees 
    on May 5, 2021 8:57 AM in reply to OomlA

    Hi Park,

    1. yes, the internal clock is 8 MHz.

    2. Please refer to the table 2 (timing specifications), figure 3 and Write Operation (pg 52) for better understanding of timing sequence.

    3. As SYNC RESETs the device, it is recommended to wait 1ms as mentioned in RESETTING THE AD4110-1 on pg 51. Please follow that to get the first /RDY pulse.

    4. Please use 1 ms wait after SYNC.


    Vikas J