AD7768-1 Raw modulator output for FPGA post-processing

Is there an option to enable a raw modulator output feature?

In the datasheet there's the flag "MOD_OUTPUT" with no clear description what it means. If this enables the modulator output on which interface pins is it available?

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  • 0
    •  Analog Employees 
    on May 18, 2021 10:19 AM

    hi

    there is mod output mode on the AD7768-1, but note that its only available in low power mode. Note that we have minimum tests on this feature

    Pseudo Algorithm would be 

    ►Configure the part via SPI as desired

    ►Put part into Modulator output mode, using MOD_OUTPUT bit in Register 0x15.

    ►Enable continuous read mode.

    ►The 8 modulator data bits are available after DRDY in address 0x2c.

    ►The first bit available to read is mod_data[7], so only 8 SCLK s are needed.

    ►DRDY will be pulsed indicating updated data, so SCLK needs to be fast enough to throw out the bits

    ►Max DRDY supported is 1.024 MHz.

    ►POWER_MODE is fixed at ECO

    thanks

Reply
  • 0
    •  Analog Employees 
    on May 18, 2021 10:19 AM

    hi

    there is mod output mode on the AD7768-1, but note that its only available in low power mode. Note that we have minimum tests on this feature

    Pseudo Algorithm would be 

    ►Configure the part via SPI as desired

    ►Put part into Modulator output mode, using MOD_OUTPUT bit in Register 0x15.

    ►Enable continuous read mode.

    ►The 8 modulator data bits are available after DRDY in address 0x2c.

    ►The first bit available to read is mod_data[7], so only 8 SCLK s are needed.

    ►DRDY will be pulsed indicating updated data, so SCLK needs to be fast enough to throw out the bits

    ►Max DRDY supported is 1.024 MHz.

    ►POWER_MODE is fixed at ECO

    thanks

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