Inquiry about the timing characteristics of the AD7703

Hi, 

I am not sure if I understand the question correctly. But after the LSB has been transmitted, DRDY and SDATA go Hi-Z. If /CS is taken high at any time during data transmission, SDATA becomes Hi-Z. 

Thanks,

Jellenie

Hi, 

Have you tried this setup and see if there's an issue? I think the 150ns is the max so it is not advisable to read it after that time. However, as I mentioned earlier the SDATA will be Hi-Z after the last LSB is transmitted. So from my understanding as long as T14 won't exceed the T16 or 150nsec timing then there should be no issue. 

But might be good to try it and to confirm this. I do not have a board with me as this is an old product but let me coordinate this with the product owner to comeback to you. 

Thanks,

Jellenie

Hi,

I'm having problems with a customer using this board.
Since the typical value for t16 is 100 nsec, wouldn't the problem occur if 100 < t14 < 150 nsec? 

Thanks,
Takahiro

Hi, 

If T16 is less than T14 yes looks like that would be an issue. But I was wondering that if the typical data for T14 is 75nsec and T16 typ data is 100nsec. Then we can use the 75nsec as a reference rather than the max timing? For a 150nsec I was thinking that T16 is expected to be 200nsec so that it is still longer than the 150nsec. What do you think? 

Thanks,

Jellenie

Hi,

I understand with regards to what you have explaining but from the customer design point of view there are problem how use these details for designing .

From customer point of view should we consider TYP or Max in either way , what is described in the data sheet is a bit confusing .

If we design our board with thinking about the worst case scenario we will not be able to read the LSB.

Eg:

T16  = TYP 100 ns and T14 =   Max 150  ns we will not be able to read the LSB.

And our customer are facing similar problem .

Best Regards,
Takahiro

Hi, 

We have coordinated this to the product owner so he can clear things up regarding this timing and how to resolve customer’s issue. We’ll come back to you on this.

Thanks,

Jellenie

HI,

Customers are in a hurry to get answers because of mass production status.
How is the progress?

Best Regards,
Takahiro

Hi, 

Apologies. I will flag this again to the product owner to get back to you on this asap. 

Thanks,

Jellenie

Hi JellenieR,

Can I have an answer?
I would appreciate it if you could tell me the situation.

Thanks,
Takahiro

Hi, 

Apologies for missing this item. May I know the status of this? 

The max numbers its suggests that 150 ns max for the data to appear after the falling edge, the t16 falling edge to high impedance is 200nS max which suggests that the data will be guaranteed for 50nS on the last clock.

So like I said previously, the typical number stated for t16 is an issue if the t14 is a max as the bus will be high impedance before the data appears.

But I think the device would never skip the LSB, and the two timing spec would probably track each other. 

Thanks,

Jellenie

Hi, 

Apologies for missing this item. May I know the status of this? 

The max numbers its suggests that 150 ns max for the data to appear after the falling edge, the t16 falling edge to high impedance is 200nS max which suggests that the data will be guaranteed for 50nS on the last clock.

So like I said previously, the typical number stated for t16 is an issue if the t14 is a max as the bus will be high impedance before the data appears.

But I think the device would never skip the LSB, and the two timing spec would probably track each other. 

Thanks,

Jellenie