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AD7703 Production
The AD7703 is a 20-bit ADC that uses a S-? conversion technique. The analog input is continuously sampled by an analog modulator whose mean output duty...
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AD7703 on Analog.com

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Inquiry about the timing characteristics of the AD7703

		            
		

			

									
					    Takahiro
					
							


			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Apr 27, 2021 
				
			
			
		
    
		
     
				
		
    
		    		    
		    
		    	
			
    Hi all,
    

    I am currently using an AD7703 in SEC Mode.
    My question is based on "Figure 5a: SEC Mode Timing Diagram" and "Figure 17: Timing Diagram for SEC Mode".
    

    For DB18 to DB0, I understand that the value of DBx becomes valid after t14 from the falling edge of the previous SCLK.
    In the case of DB0(LSB), when t14(max)=150 nsec and t16(typ.)=100 nsec, under the worst case condition, it seems to become Hi-Z before getting the value of DB0.
    

    Please tell me the conditions under which SDATA becomes Hi-Z.
    

    Best Regards,
    Takahiro
    

    

    

    

    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 Single Channel A/D Converters
                
                                                    
                 adc
                
                                                    
                 spi
                
                                                    
                 AD7703
                
                                                    
                 Precision A/D Converters
                
                                
            
    
    
    

		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      •  Super User  
      
            
						
                            
            
            				
            
                on Apr 28, 2021 1:48 AM
            
                                    
					
      
	
      

		
		
      
					
      Hi,
      

      We will look into this, I'll contact the product owner and get back to you.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
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                on Apr 28, 2021 6:54 AM
            
                                    
					
      
	
      

		
		
      
					
      Hi, 
      

      I am not sure if I understand the question correctly. But after the LSB has been transmitted, DRDY and SDATA go Hi-Z. If /CS is taken high at any time during data transmission, SDATA becomes Hi-Z. 
      

      Thanks,
      

      Jellenie
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
						
						
				
				
		
		
      
			
		
      
	
      

      

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                on Apr 28, 2021 7:51 AM
            
                                    
												
						in reply to JellenieR
					
									
        
	
        

		
		
        
					
        

        

        

        Hi, Jellenie
        

         
        

        Thanks for the answer.
        

         
        

        For example, assume that SCLK is transmitted 19 times after waiting "t13" from the falling edge of CS.
        

        DB0 is observed on SDATA after t14 from the last SCLK (19th SCLK).
        

        In this case, to satisfy the maximum value of t14 (150 nsec max), we configure the system to wait 160 nsec to read the data.
        

        However, the typical value for t16 is 100 nsec, so we figured it might change to Hi-Z before reading the data.
        

         
        

        So, could you please tell me the appropriate timing for reading data?
        

         
        

        Best Regards,
         Takahiro
        

        

        

        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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        •  Analog Employees  
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                on Apr 29, 2021 2:20 AM
            
                                    
												
						in reply to Takahiro
					
									
        
	
        

		
		
        
					
        Hi, 
        

        Where exactly do you put the delay of the 160nsec? T14 must not exceed 150nsec so it falls within the max T16 of 200ns. So if T16 is 100ns the typical T14 is 75nsec typical which is still within T16, meaning the data supposed to be read before SDATA becomes tri-stated. 
        

        Thanks,
        

        Jellenie
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Apr 29, 2021 7:42 AM
            
                                    
												
						in reply to JellenieR
					
									
          
	
          

		
		
          
					
          

          

          

          Hi,
          

           
          

          Suppose that the FPGA is set to read SDATA after 150nsec from the falling edge of SCLK in order to satisfy the maximum value of t14.
          

          At this time, if t16 is the standard value of 100nsec, isn't it possible to read SDATA?
          

           
          

          Thanks,
          

          Takahiro
          

          

          

          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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          •  Analog Employees  
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                on Apr 30, 2021 12:29 AM
            
                                    
												
						in reply to Takahiro
					
									
          
	
          

		
		
          
					
          Hi, 
          

          Have you tried this setup and see if there's an issue? I think the 150ns is the max so it is not advisable to read it after that time. However, as I mentioned earlier the SDATA will be Hi-Z after the last LSB is transmitted. So from my understanding as long as T14 won't exceed the T16 or 150nsec timing then there should be no issue. 
          

          But might be good to try it and to confirm this. I do not have a board with me as this is an old product but let me coordinate this with the product owner to comeback to you. 
          

          Thanks,
          

          Jellenie
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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                on Apr 30, 2021 12:45 AM
            
                                    
												
						in reply to JellenieR
					
									
            
	
            

		
		
            
					
            Hi,

            I'm having problems with a customer using this board.
            Since the typical value for t16 is 100 nsec, wouldn't the problem occur if 100 < t14 < 150 nsec? 

            

            Thanks,
            Takahiro
            

            

            

            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
				
						
				
				
		
		
            
			
		
            
	
            

            

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            •  Analog Employees  
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                on Apr 30, 2021 1:03 AM
            
                                    
												
						in reply to Takahiro
					
									
            
	
            

		
		
            
					
            Hi, 
            

            If T16 is less than T14 yes looks like that would be an issue. But I was wondering that if the typical data for T14 is 75nsec and T16 typ data is 100nsec. Then we can use the 75nsec as a reference rather than the max timing? For a 150nsec I was thinking that T16 is expected to be 200nsec so that it is still longer than the 150nsec. What do you think? 
            

            Thanks,
            

            Jellenie
            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
				
						
				
				
		
		
            
			
		
            
	
            

            

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                on Apr 30, 2021 6:52 AM
            
                                    
												
						in reply to JellenieR
					
									
              
	
              

		
		
              
					
              Hi,
              

              I understand with regards to what you have explaining but from the customer design point of view there are problem how use these details for designing .
              

              From customer point of view should we consider TYP or Max in either way , what is described in the data sheet is a bit confusing .
              

              If we design our board with thinking about the worst case scenario we will not be able to read the LSB.
              

              Eg:
              

              T16  = TYP 100 ns and T14 =   Max 150  ns we will not be able to read the LSB.
              

              And our customer are facing similar problem .
               
               Best               Regards,
               Takahiro
              
			
              

		
			
	      

		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

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              •  Analog Employees  
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                on Apr 30, 2021 11:01 AM
            
                                    
												
						in reply to Takahiro
					
									
              
	
              

		
		
              
					
              Hi, 
              

              We have coordinated this to the product owner so he can clear things up regarding this timing and how to resolve customer’s issue. We’ll come back to you on this.
              

              Thanks,
              

              Jellenie
              
			
              

		
			
	      

		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

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