AD4004 3-Wire Turbo Mode

Thanks for your queries, see responses below your quoted questions:

MZielinski said:

Does sending the register access command and the register data on SDI prevent a normal conversion from occurring?

No, the AD4004 will still perform a sample on CNV rising edge prior to sending the Register Access Command. For example, in Figure 48, the CNV rising edge pictured still triggers the ADC to sample the input, and you can see the  ADC data output on SDO (D15 - D0).

MZielinski said:

How does the AD4000 determine whether it is in register read/write mode, 3-wire mode, or 4-wire mode?

In short, if SDI is HIGH during CNV Rising Edge, then the device will enter either 3-Wire or 4-Wire mode. The device then selects between 3- and 4-Wire Modes based on the state of CNV while SCK is active. If CNV is brought back LOW then the device is put into 3-Wire Mode and 3-Wire Mode supports both ADC Data Readback and Register Writes.

This isn't explicitly stated in the data sheet so I can understand the confusion, but basically you could follow the CNV timing shown in the 3-Wire Without Busy Indicator section (Figure 54) but instead of holding SDI HIGH, you could send the Register Access Command and Register Data over SDI as pictured in Figure 48, and effectively write to the Configuration Register at the same time as clocking out the data.

This answers your other question:

MZielinski said:

In other words, must I send the configuration data once before use, and then keep SDI high during normal ADC conversion operation?

The answer is technically no, for the reasons explained above.

However, if the AD4004 is interfacing with a "standard" SPI peripheral with CNV tied to an active-low chip-select/slave-select line, then the data that is output on SDO in the first frame may not be an actual valid conversion result. This just depends on whether the chip-select line is LOW or HIGH when the AD4004 power-up routine finishes. But it's simpler in practice to ignore the "ADC Data" on the first SPI frame in this case and to wait for the second SPI frame to read back data, in order to be sure that CNV rising edge was registered by the device.

This is why we separated the Register Read/Write functionality from the ADC Data Read (i.e. 3-Wire Without Busy Indicator, etc.) functionality in the AD4004 data sheet - because we assumed that the above use case would be the most common, and it was simpler to describe these as being two separate "modes".

MZielinski said:

On page 30, the AD4000/4004/4008 datasheet says this about 3-Wire Without Busy Indicator mode, "When performing conversions in this mode, SDI must be held high." But on the same page, under Figure 53, it says "SDI must be connected to the digital host data out to write to the configuration register." This seems like a contradiction; could anyone please provide an answer to these questions I have?

This instruction to hold SDI HIGH throughout the ADC data readback in "3-Wire Without Busy Indicator" mode is technically not required, for the reasons stated above. You may choose to send the configuration register data over SDI while reading the ADC Data on SDO. As described above, the reason that this "requirement" was written out was to simplify the overall documentation of the AD4004 interface based on our assumptions of the most common use-cases. I still recommend to treat the Register Write as a separate function from the ADC Data Readback in general.

Hopefully that addresses your core questions. Feel free to reply to this comment with any follow-up questions or if I need to clarify anything.

Thanks,

Tyler

Thanks for your queries, see responses below your quoted questions:

MZielinski said:

Does sending the register access command and the register data on SDI prevent a normal conversion from occurring?

No, the AD4004 will still perform a sample on CNV rising edge prior to sending the Register Access Command. For example, in Figure 48, the CNV rising edge pictured still triggers the ADC to sample the input, and you can see the  ADC data output on SDO (D15 - D0).

MZielinski said:

How does the AD4000 determine whether it is in register read/write mode, 3-wire mode, or 4-wire mode?

In short, if SDI is HIGH during CNV Rising Edge, then the device will enter either 3-Wire or 4-Wire mode. The device then selects between 3- and 4-Wire Modes based on the state of CNV while SCK is active. If CNV is brought back LOW then the device is put into 3-Wire Mode and 3-Wire Mode supports both ADC Data Readback and Register Writes.

This isn't explicitly stated in the data sheet so I can understand the confusion, but basically you could follow the CNV timing shown in the 3-Wire Without Busy Indicator section (Figure 54) but instead of holding SDI HIGH, you could send the Register Access Command and Register Data over SDI as pictured in Figure 48, and effectively write to the Configuration Register at the same time as clocking out the data.

This answers your other question:

MZielinski said:

In other words, must I send the configuration data once before use, and then keep SDI high during normal ADC conversion operation?

The answer is technically no, for the reasons explained above.

However, if the AD4004 is interfacing with a "standard" SPI peripheral with CNV tied to an active-low chip-select/slave-select line, then the data that is output on SDO in the first frame may not be an actual valid conversion result. This just depends on whether the chip-select line is LOW or HIGH when the AD4004 power-up routine finishes. But it's simpler in practice to ignore the "ADC Data" on the first SPI frame in this case and to wait for the second SPI frame to read back data, in order to be sure that CNV rising edge was registered by the device.

This is why we separated the Register Read/Write functionality from the ADC Data Read (i.e. 3-Wire Without Busy Indicator, etc.) functionality in the AD4004 data sheet - because we assumed that the above use case would be the most common, and it was simpler to describe these as being two separate "modes".

MZielinski said:

On page 30, the AD4000/4004/4008 datasheet says this about 3-Wire Without Busy Indicator mode, "When performing conversions in this mode, SDI must be held high." But on the same page, under Figure 53, it says "SDI must be connected to the digital host data out to write to the configuration register." This seems like a contradiction; could anyone please provide an answer to these questions I have?

This instruction to hold SDI HIGH throughout the ADC data readback in "3-Wire Without Busy Indicator" mode is technically not required, for the reasons stated above. You may choose to send the configuration register data over SDI while reading the ADC Data on SDO. As described above, the reason that this "requirement" was written out was to simplify the overall documentation of the AD4004 interface based on our assumptions of the most common use-cases. I still recommend to treat the Register Write as a separate function from the ADC Data Readback in general.

Hopefully that addresses your core questions. Feel free to reply to this comment with any follow-up questions or if I need to clarify anything.

Thanks,

Tyler

Thank you for the very thorough answer, I really appreciate it. I think everything is clear now. One quick follow up question: is everything you wrote also true in Turbo mode?

I'm also glad you mentioned that

tschmitt said:

if the AD4004 is interfacing with a "standard" SPI peripheral with CNV tied to an active-low chip-select/slave-select line

I haven't seen this kind of usage before, but thinking about it now it seems obvious. It's almost strange that the datasheet never shows CS connected to CNV.

Thanks again.

MZielinski said:

One quick follow up question: is everything you wrote also true in Turbo mode?

Yes, at least for the 3-Wire Turbo Mode option.

MZielinski said:

I haven't seen this kind of usage before, but thinking about it now it seems obvious. It's almost strange that the datasheet never shows CS connected to CNV.

The only warning I should have given with this approach is regarding jitter on SPI Controller CS outputs.

In general, the faster the analog input signal that is being measured, the more jitter will degrade overall performance (typically jitter manifests as noise, at least if it is Gaussian in nature).

And since convert-start is triggered on CNV rising edge, you'll want to consider the jitter of the CS rising edges "period" - I don't know how well this timing can be controlled on a typical microcontroller.

So if your system needs very low jitter then you may consider using a TIMER peripheral instead of SPI's CS line for CNV. But again, depends on the capabilities of your host system.

It seems I've gotten off topic here, but hopefully this is useful information!

-Tyler

Thanks Tyler, not off topic at all. I'm glad you confirmed my own reasoning about using CS for CNV. I myself started out with using a TIMER to generate CNV and will continue to do so for the sake of jitter, as you said.

It's not really an issue, but it appears that I'm in fact not able to read out a valid conversion and perform a register write in the same transfer.

When writing, I read out either 0x8014 or 0x0014 (varies only in the MSB that is output on CNV falling edge). The 0x014 value does not seem to change with register contents.

When reading register contents after a reset I read out either 0x8161 or 0x0161 (again depending on the MSB that is output on the CNV falling edge). The lower 5 bits do correspond to the non-reserved register bits (if I read after setting bit 3, span compression enable, I read either 0x8169 or 0x0169, and the span does actually get compressed). Bits 7-5, which are marked reserved with a reset value of 0x0 in the datasheet, do not actually seem to be all set to 0. 

I can't see any of this being a problem, I just wanted to note down my observations for anyone else who finds this thread. But I will have to first configure the register, and then keep SDI held high like I originally though.

Thanks,

-Mike