About the AD7380/16bit SDOA data no signal output problem

Hi Steven,

             Based on these photos, the SCLK signals are fine. How is the CS signal? The AD7380 requires the CS to initiate the conversion. What is the voltage level on the input? The output of the AD7380 is two's complement. Would it be possible to vary the input and check the SDO line if the output also changes, with the digital signal also running the especially the SCLK and CS lines. This should at least have an output seen on the SDO lines.

Regards,

Jonathan

Hi Jonathan,

Thank you for your reply.
I checked the AD7380 component solder not good on the board. Because I re-soldering it.
I found that it can output the "SDOA" signal.

I have tried to use the initial AD7380.

0x0000,0x2000,0xA1FFF,02000

But read back AD7380 is " 0x0000 ".

CPOL = 1，CPHA = 0 

Thank you in advance for your help.

Hi Steven,

        It is good that you are now seeing the SDOA.

        Just a clarification, the readback is from what register? Register 0x1, 0x2 and 0x3 are default value at 0. While 0x4 and 0x5 have 0x0800 and 0x07FF respectively.  What are these data, 0x0000,0x2000,0xA1FFF,02000? are these conversion results. based on what you mentioned, all registers from the AD7380 are set at default. Is this correct? If you can try writing to the part and perform readback would be a good test.

Regards,

Jonathan

Hi Jonathan,

Based on your suggestion and checked, I have successfully read and written it. 

I have another ADC converter LSB question.

For example:
The size is (2 × VREF)/2^N, where N is the ADC resolution.
Vref=3.3V
N= 16bit (65535)
(2x 3.3v)/2^N(16bit) = 100.7μV 

But I checked the AD7380 document alert Low and High, Data Bits [D11:D0] is 12bit.

If to reads ADC converter Reg "0x7FF" or "0x800", which is 2^12 = 4096 is right?

So ADC resolution is 12 bit not 16bit?

How to convert the register value to alignment resolution data?

I am confused about it.

Please let me know if there is something wrong.

Thank you in advance for your help.

Hi Jonathan,

Based on your suggestion and checked, I have successfully read and written it. 

I have another ADC converter LSB question.

For example:
The size is (2 × VREF)/2^N, where N is the ADC resolution.
Vref=3.3V
N= 16bit (65535)
(2x 3.3v)/2^N(16bit) = 100.7μV 

But I checked the AD7380 document alert Low and High, Data Bits [D11:D0] is 12bit.

If to reads ADC converter Reg "0x7FF" or "0x800", which is 2^12 = 4096 is right?

So ADC resolution is 12 bit not 16bit?

How to convert the register value to alignment resolution data?

I am confused about it.

Please let me know if there is something wrong.

Thank you in advance for your help.

Hi Steven,

         Apologies for this confusion. Regarding the ALERT_LOW and ALERT_HIGH thresholds. The default values are set at 0x800 and 0x7FF. These default values are MSBs, the remaining 4 LSBs as mentioned briefly in the second sentence of the description are 0x0 for Alert low threshold and 0xF for the high threshold that completes the total to 16 bits.

Regards,

Jonathan

Hi Jonathan,

Thank you for your reply and clarification.

I understand Reg-0x04/0x05 the default values set are 0x800 and 0x7FF.

I checked the ADC converter read values are 0x7FFF and 0x8000.

when Ain+, Ain- = 3.3v / Gnd = 0x7FFF

         Ain+, Ain- = Gnd / 3.3v = 0x8000

Therefore, the ADC is 16bit.

Thank you again for your kind answers!

Hi Jonathan, 

I have a question about the SPI CLK operating Fq range of the AD7380?

If DSP the SIP high speed mode fq 10Mhz～50Mhz (max), when AD7380 can support 4MSPS?

Thanks.

Hi Jonathan,

I'm to bother you again.
I have hardware questions for SPI 2 write mode to connect.
In AD7380 the "SDOB" and "SDOA" pin.
How to read the "SDOB" method and hardware connect to MCU SPI not understand.

C2000-MCU (SPI-A) ---> (AD7380)
SCLK ---> SCK
SDIN ---> SDIN
SDOUT ---> SDOA
CS ---> CS
GPIO ---> SDOB

(SPI-B) ---> (AD7380)
SCLK ---> SCK
SDIN ---> SDIN
SDOUT ---> SDOB
CS ---> CS

Could you help answer these questions?
Thank you!

Hi Steve,

        The AD7380 is specified to run at 80Mhz SCLK. At this clock rate, 4MSPS can be achieved. Running at 50MHz would allow a slower time reading the conversion results. At 50Mhz SCLK, the throughput rate can be around 3MSPS throughput rate.

Regards,

Jonathan