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AD7760,DRDY always at low

Hello, I am now working on a project development, using AD7760. Now I'm testing the AD7760 evaluation board. The power supply and clock of the evaluation board are normal. The SYNC signal is always high. My test process is to write reg2_add=0h0002, to reg2_data=0h0002, and then set the CS and RD/WR signals to high level. The attached picture is the waveform of each signal on the evaluation board tested by me with an oscilloscope. Among them, blue represents CS signal, yellow in figure 1 is MCLK signal, yellow in figure 2 indicates RESET signal, yellow in figure 3 indicates DB1 signal, yellow in figure 4 indicates RD/WR signal, and other DB signals have been zero. But the result is that the DRDY signal is always at a low level. In urgent need of help: what other tests can I do?


  • Hi, 

    Thank you for posting. First, I'll move this query to Precision ADCs. 

    I'll contact the product owner to assist you. However, I have few clarifications. 

    For your /RD/WR signal is that high or low? Have you tried to pull /CS and /RD/WR low and did you noticed that DB1 is always 1? Does it means the ADC must be saturated? Can you also confirm that both /SYNC and RESET pin are driven high? 

    May I know what is your input voltage, reference voltage used? And are you using the mod input or the VIN inputs? Though I am assuming with correct MCLK and VREF, and both /SYNC and RESET pin are both high, the the DRDY pin should be pulsing at correct ODR. 

    Again, I'll let the product owner further assist you. 




    I'm sure /RD/WR=1,/SYNC=1,RESET=1.DB1 is not always 1.



  • Hi, 

    Have you changed /RD/WR = 0. I think this should be low and the same with /CS if you wanted to read the conversions. 

    I have contacted the product, but I'll follow him up to get back to you. 



  • I have found the cause of the problem. The RESET signal is too long. Datasheet requires that the reset signal should not be less than 1 mclk cycle. But my reset signal lasts for half a second. Causes AD not to start properly. After modifying the reset signal to 2 mclk cycles, the AD can work normally and the DRDY signal can be output normally. The correct signal has been picked up. Thank you

  • Great to hear that you have solved the issue Thanks also for sharing. Slight smile



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