I have a lab measurement application that requires fast sampling with high DC accuracy. For the ADC we have selected the LTC2380-24 with a 5 V reference input voltage (derived from an LTZ1000 reference). The input voltages will be sampled in bursts at a rate of 1 MSPS.
For designing and modeling the reference buffer and its settling performance, I understand that the current draw at the ADC REF pin can best be modeled as a series of successively smaller switched capacitor loads during the conversion step. Unfortunately the datasheet does not detail this behavior, like it does for the ADC inputs.
Is it possible to provide additional information as to what the timing looks like for these switched capacitor loads, and how large these successive loads are?