other question about my new project with 16 AD7771 in a single board.
I need to interface 16 ADCs with a FPGA saving lines. The sampling process will be simoultaneus than I have to read data from ADCs.
I'll use SPI bus also for read back sigma delta data. Two possible solutions, but I don't know if applicable:
1) Share CS and SCLK lines and dedicated SDI/SDO lines for each ADC -> It is possible share CS line? This is the only concern about this solution.
2) Share SDI/SDO/SCLK lines and dedicated CS line for each ADC -> In this solution the FPGA must write and read in series 8 channels from 16 ADCs, but if this process is slower than conversion time, unread data should be corrupted and lost.
Any advice about this solutions? I'd like the first if applicable, the reading process should be simultaneous.