LTC2386-16
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The LTC2386-16 is a low noise, high speed, 16-bit 10Msps successive approximation register (SAR) ADC ideally suited for a wide range of applications. The...
Datasheet
LTC2386-16 on Analog.com
Hi,
I am planning to use LTC2386-16 ADC in my design. I have query on Data Clock outputs (DCO+ and DCO-) and Clock input (CLK+ and CLK-) pins of ADC.
Shall i use Any LVDS I/O pins of FPGA to interface ADC data clock o/ps (DCO+ and DCO-) and Clock signals (CLK+ and CLK-)?
Or Is it mandatory to use FPGA clock signals for both interfacing.
Regards,
Malathi T
Hi,
We will look into this, I'll contact the product owner and get back to you.
Regards,
Andrei
Hi Malathi,
The LTC2386 doesn't care if you use the CLK FPGA pins but the FPGA may care.
Hi ghoover,
I am not clear can you provide detailed explanation.
You mean if i configure CLK+ and CLK- signal as IO output from FPGA. Will it work?
You should probably talk to the FPGA support people to confirm this but my understanding is any LVDS lines from the FPGA can be used to drive the CLK+ and CLK- lines. They do not have to be designated clock lines. The ADC only cares that the voltage levels are correct.