AD7770 Data output interface

Hello,

I have problems understanding data output interface on AD7770. Here is my ADC config sequence:

08 8C (Channel disable)
11 7C (General user config 1)

13 C0 (General user config 3)

14 82 (Dout format)

60 03 (SRC N MSB)

61 D0 (SRC N LSB)

62 90 (SRC IF MSB)

Master clock 8MHz, synchro clock 2.048kHz. I am trying reading Sigma-Delta data with data output interface. I thought I can treat Dout0 as MOSI, Dclk as serial clock, and Drdy as chip select, and read it with SPI slave component on MCU. Here is what I am getting. Currently nothing is connected to positive analog (negative analog is grounded). But I am expecting stable 2.048ksps on Drdy - and it is not. Does anyone understand this data dump? Does anyone see what am I doing wrong?

  • Okay, good news is I got ADCs configured. Also I am getting 4MHz on DCLK.

    Bad news is I got nothing on DOUT0 and DRDY.

    How am I supposed to start conversions?

  • 0
    •  Analog Employees 
    on Feb 20, 2021 10:50 AM in reply to maskrtnik01

    Hi Stanislav,

    That´s good. So, now when you read through DOUT do you get the headers properly but the 24 bit data are all 00? Note the disabled channels should show 00.

    Have you check for error flags if any is asserted?

    If MCLK is properly applied (it probably is if DCLK is correct), you should see DRDY toggling straightaway unless the device is in RESET state (check RESET pin or SYNC_IN pin) or shutdown mode.

    Regards,

    Lluis.

  • Hello Lluis,

    No, I get stable 4MHz on DCLK. But DRDY and DOUT0 are idle. Sounds like conversion hasn't started - what do you think?

    I will check status registers.

    Also I have made one change. Before I was starting synchro clock after configuration. Now I have started synchro clock on mcu boot. Does this matter?

    One last thing. How should ADC behave, when positive input is floating? Could it suppress output due to DSP error?

    Stanislav

  • Register value asserted flags
    CH0STAT 10 negative undervoltage
    CH1STAT 10 negative undervoltage
    CH2STAT 14 negative undervoltage, negative overvoltage
    CH3STAT 14 negative undervoltage, negative overvoltage
    CH4STAT 10 negative undervoltage
    CH5STAT 10 negative undervoltage
    CH6STAT 14 negative undervoltage, negative overvoltage
    CH7STAT 14 negative undervoltage, negative overvoltage
    CH01SATERR 00 none
    CH23SATERR 00 none
    CH45SATERR 00 none
    CH67SATERR 00 none
    ERR1 00 none
    ERR2 00 none
    STAT1 33 chip error, ch4 error, ch1 error, ch0 error
    STAT2 23 chip error, ch6 error, ch5 error
    STAT3 30 chip error, init complete

    First thing I really don't understand, how could I get both undervoltage and overvoltage on an input.

    Second, what is proper way to make inputs single-ended? I have grounded negative inputs.

    Stanislav

  • 0
    •  Analog Employees 
    on Feb 20, 2021 5:07 PM in reply to maskrtnik01

    Hi Stanislav,

    Yes, you could have both OV and UV flagged. As you can see on AN-1405 (Rev. A) (analog.com), the flag asserts when the OV/UV occur and won´t clear till the register is read back. You are tying AINM to GND, but what´s your AVSS? It´s strange if tying it to ground goes beyond AVDD. Have you sanity checked AVDD1 and AVDD2 pins?

    How about the SYN_IN pin?

    Regards,

    Lluis.