AD7770 Data output interface

Hello,

I have problems understanding data output interface on AD7770. Here is my ADC config sequence:

08 8C (Channel disable)
11 7C (General user config 1)

13 C0 (General user config 3)

14 82 (Dout format)

60 03 (SRC N MSB)

61 D0 (SRC N LSB)

62 90 (SRC IF MSB)

Master clock 8MHz, synchro clock 2.048kHz. I am trying reading Sigma-Delta data with data output interface. I thought I can treat Dout0 as MOSI, Dclk as serial clock, and Drdy as chip select, and read it with SPI slave component on MCU. Here is what I am getting. Currently nothing is connected to positive analog (negative analog is grounded). But I am expecting stable 2.048ksps on Drdy - and it is not. Does anyone understand this data dump? Does anyone see what am I doing wrong?

Parents
  • Okay, good news is I got ADCs configured. Also I am getting 4MHz on DCLK.

    Bad news is I got nothing on DOUT0 and DRDY.

    How am I supposed to start conversions?

  • 0
    •  Analog Employees 
    on Feb 20, 2021 10:50 AM in reply to maskrtnik01

    Hi Stanislav,

    That´s good. So, now when you read through DOUT do you get the headers properly but the 24 bit data are all 00? Note the disabled channels should show 00.

    Have you check for error flags if any is asserted?

    If MCLK is properly applied (it probably is if DCLK is correct), you should see DRDY toggling straightaway unless the device is in RESET state (check RESET pin or SYNC_IN pin) or shutdown mode.

    Regards,

    Lluis.

  • 0
    •  Analog Employees 
    on Feb 21, 2021 9:24 AM in reply to maskrtnik01

    Hi Stanislav,

    By sanity check I meant to take the multimeter and just make sure all pins are at the level we expect i.e. RESET, START and SYNC_IN at logic high, AVDD1 and AVDD2 at 3.3V, etc. These are the pins that, being at the wrong level, could prevent the DRDY to toggle.

    According to the flags, your AINM pins are going below AVSS, can you doble check that too? are they just tied to the ground plane or any other connection that could be pulling these inputs to lower voltage?

    Regards,

    Lluis.

  • Hello Lluis,

    I have probed all I can. Unfortunately, I don't have test points for signal lines. And with package size, I would definitely short something. I don't have time nor money for another iteration.

    ==========IC2========
    6-AVDD1A 3.289V
    8-REF1+ 2.047V
    23-DREGCAP 1.803V
    24-IOVDD 3.289V
    41-REF2+ 2.047V
    43-AVDD1B 3.289V
    49-REFOUT 0V
    51-AREG2CAP 1.904V
    52-AVDD2B 3.289V
    57-VCM 0V
    58-AVDD2A 3.289V
    59-AREG1CAP 1.908V
    62-AVDD4 3.289V
    ==========IC1========
    6-AVDD1A 3.289V
    8-REF1+ 2.047V
    23-DREGCAP 1.802V
    24-IOVDD 3.289V
    41-REF2+ 2.047V
    43-AVDD1B 3.289V
    49-REFOUT 0V
    51-AREG2CAP 1.906V
    52-AVDD2B 3.289V
    57-VCM 0V
    58-AVDD2A 3.289V
    59-AREG1CAP 1.904
    62-AVDD4 3.289V

  • I have soldered subboards, this connected instrumentation amps to positive inputs. Here are updated status registers:

    14 CH0STAT negative undervoltage, negative overvoltage
    14 CH1STAT negative undervoltage, negative overvoltage
    14 CH2STAT negative undervoltage, negative overvoltage
    14 CH3STAT negative undervoltage, negative overvoltage
    14 CH4STAT negative undervoltage, negative overvoltage
    14 CH5STAT negative undervoltage, negative overvoltage
    14 CH6STAT negative undervoltage, negative overvoltage
    14 CH7STAT negative undervoltage, negative overvoltage
    00 CH01SATERR none
    00 CH23SATERR none
    00 CH45SATERR none
    00 CH67SATERR none
    00 ERR1 none
    00 ERR2 none
    33 STAT1 chip error, ch4 error, ch1 error, ch0 error
    23 STAT2 chip error, ch6 error, ch5 error
    30 STAT3 chip error, init complete

    For some reason, STAT1 and STAT2 report error on used inputs, unused inputs (both positive and negative grounded) are not reported.

    Maybe, I have joined analog and digital ground with ferrite beads. I can measure with multimeter, that DGND = AGND + 2mV. However, there could theoretically be some noise - could this cause UV and OV to happen? Should I desolder ferrite beads, and short-circuit grounds to equal potential?

  • Got It! Too fast synchro clock was apparently preventing any successful conversion.

    What is optimal sync clock to a given sample rate?

    One last problem, DRDY is not absolutely stable, each few samples I get a gap. That would interfere with frequency-domain analysis, and this is my goal.

Reply Children
  • +1
    •  Analog Employees 
    on Feb 24, 2021 9:26 AM in reply to maskrtnik01

    Hello,

    How are you using the SYNC signal so? The AD7770 is a sigma delta ADC so it will continuously run conversion managed by MCLK. SYNC_IN is just a synchronization input, that you may eventually issue if your DRDY is out out sync of a given synchronization signal. I don´t know the details of you application, but I would not understand the SYNC_IN as a signal to be applied at a given frequency but a interruption to be launch only under certain conditions.

    Regards,

    Lluis.

  • Yes I have noticed, that the slower synchro clock, the less frequently I get a gap.

    Well, it´s different than I have expected. What I want at the end, is to synchronize 2 ICs. I need 10 channels, so I have added 2 ICs to board design, 5 channels each.

    I have worked previously with Maxim's MAX11254. It's Sigma-Delta too, although multiplexed. Anyway, at synchro input it expects a continuous signal with frequency, that is a multiple of sampling frequency.