AD7770 Data output interface

Hello,

I have problems understanding data output interface on AD7770. Here is my ADC config sequence:

08 8C (Channel disable)
11 7C (General user config 1)

13 C0 (General user config 3)

14 82 (Dout format)

60 03 (SRC N MSB)

61 D0 (SRC N LSB)

62 90 (SRC IF MSB)

Master clock 8MHz, synchro clock 2.048kHz. I am trying reading Sigma-Delta data with data output interface. I thought I can treat Dout0 as MOSI, Dclk as serial clock, and Drdy as chip select, and read it with SPI slave component on MCU. Here is what I am getting. Currently nothing is connected to positive analog (negative analog is grounded). But I am expecting stable 2.048ksps on Drdy - and it is not. Does anyone understand this data dump? Does anyone see what am I doing wrong?

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  • 0
    •  Analog Employees 
    on Feb 15, 2021 11:05 AM

    Hello,

    Well, that´s not exactly the way you´d operate it. Note that when using the DOUT interface, the AD7770 is the master and not your controller. So, you have to make sure your controller is not pulling the CS and the SCLK lines, AD7770 should drive them and the controller have them as inputs.

    DRDY will not toggle at your modulator frequency (MCLK/4), DRDY will toggle at mod_freq/SRC. See page 52.

    Im trying to look for the headers. On the second DRDY pulse I see 81, that could match with channel 0 if ALERT bit is set. Then 92 that could match with ch 1 if ALERT bit is set. But then after that channel all looks to be 0x00. What´s the difference between DOUT0 and MISO line?

    Are you reading back registers on SDO to make sure that what you wrote matches what you read?

    Regards,

    Lluis.

  • Hello Lluis,

    Thanks for reply. I understand that on data interface, AD7770 is the master. I am not trying to drive DCLK/DRDY. I am simply trying to isolate individual packets by feeding DRDY to SS input of SPI slave.

    As for the frequencies, I am driving clock input with 8MHz. I have set SRC registers currently for 1.024ksps (I have lowered this in hope, that it will solve the problem - didn't). For DCLK frequency, I am trying to set it with DCLK_CLK_DIV in DOUT_FORMAT register. I need it at 4MHz or lower, otherwise SPI slave component on MCU side is not operable. Whatever I set in this field, I am still getting 8MHz on DCLK.

    I have connected MISO of SPI slave directly to DOUT0, I wonder too why DCLK is discontinuous, and why there are so many 0x00s.

    I have not yet tried to read back registers. I have probed this sequence on logic analyzer, and it looks correct.

    Regards,

    Stanislav

    EDIT: Now I have noticed, that I have setup DOUT0 line as MISO in logic analyzer settings. In fact, it is MOSI - from AD7770 to MCU.

  • 0
    •  Analog Employees 
    on Feb 15, 2021 1:59 PM in reply to maskrtnik01

    Hello,

    If you have written the DCLK_DIV and it not change and you have changed the SRC and the DRDY does not change, it looks like the write operation does not occur properly. Or, that the device is reset and the default configuration loaded.

    Can you please try to read the register you wrote to make sure the configuration is properly set?

    It´d be good if you can sent the logic analyzer scope shots too.

    Thanks,

    Lluis.

  • Hello Lluis,

    SRC is probably acting properly.

    I have read back entire register space, I see some weirdness. Could it be AD7770 malfunction? Or is it for sure communication failure?

    AD7770 should not be in reset. I am driving RESET high after SPI initialization. And in fact, it is trying to send something on dout interface.

    Regards,

    Stanislav

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