Still having Issues with Multiple Channels on the AD4115 in Continuous Read Mode

I thought I had this problem figured out but it has returned. I'm using an EVAL-AD4114/15SDZ. Clock is internal and reference is external. SPI clock is 8Mhz.

Steps to reproduce problem:

  1. Reboot ADC by writing 64 ones to DI pin with CS low
  2. Wait 1-2msec and raise CS
  3. Confirm reset by performing read of ID Register
  4. Write 0x1300 to SETUP0 (Channel 1 is set to measure inputs 0 and 1 differentially after reset but the buffers need to be enabled)
  5. Write 0x0005 to the FILTER0 register to set the sampling rate to 25,000 SPS
  6. Write 0x9043 to CHAN1 register to enable, select setup 1, and set the MUX to VIN2, VIN3
  7. Write 0x1300 to SETUP1
  8. Write 0x0005 to the FILTER1
  9. Write 0x0000 to the ADCMODE
  10. Write 0X00C0 to IFMODE to start continuous read and append status to output

In my code when the RD line goes low I clock in 32 bits. I'm seeing channel 0 on my logic analyzer with valid data followed 145uSec later by another channel 0 reading. If this was working correctly, there would be a new reading every 72.5uSec with channel 0 alternating with channel 1. From the timing, it -looks- like the ADC is doing a conversion on channel 1 but not driving the RD signal. As always, I can send lots of pretty pictures but I think the description is sufficient for now. One other twist to this story: if I set the CHAN1 MUX to VIN3,VIN2, the ADC starts outputting the data from channel 1 - it's the negative of my input but at least it's coming in. I'm getting a little nervous about using this device in my product if a repeatable solution cannot be found.

 

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  • 0
    •  Analog Employees 
    on Feb 4, 2021 12:02 AM

    Hi, 

    Apologies, I'm not sure if you answered this question already. But just wanted to confirm again, When monitoring the DRDY pin did you pull /CS low? I mean after supplying the 32 SCLKs did you put your /CS high or does it remains low all the time?

    Just another quick question, is it only a typo in step 4 that you use channel 1 for VIN0, VIN1? and then at the same time you use again CH1 for VIN2, VIN3? 

    I agree with you that enabling 2 channels must pulse the DRDY every 72.5uS. It will go high a little short time when updating the data register and then returns low once completed. 

    I remember I've tried enabling continuous read mode on my board and the DRDY pin is pulsing at correct ODRs. Let me check the above settings and come back to you. 

    I will also moving this to Q&A section so I can easily view this and response to this if needed. 

    Thanks,

    Jellenie

  • In continuous read mode I keep CS low just like the data sheet shows in figure 43 on page 41.

    My apologies - in step 4 I meant to say Channel 0.

    And there should be a step 11 which is "Set CS low and start monitoring the DOUT/RD signal.

    1. If I enable CHAN0 and CHAN1 and start continuous read without clocking out the data, I see a pulse train on MISO/RD that indicates that both channels are being converted based on the timing.
    2. If I clock out the data, the RDY pulse from CHAN1 disappears and the data indicates I'm only seeing CHAN0 data.
    3. If I only enable CHAN1 before starting continuous read, no pulses appear on RDY
  • 0
    •  Analog Employees 
    on Feb 7, 2021 6:14 AM in reply to WallyBalls

    Hi. 

    1. This confirms that the ADC is really converting at expected ODR. So there could be some issues with the SPI transactions that missing the RDY signal of the second conversion. I was thinking at first if how long did you supply SCLKs after DRDY pin goes low. 

    2. I've tried this on my EVB and it still works okay. I can send a screenshot to you if you wish too.

    3. It also works fine for me. So I'm curious what might have causing your DRDY pin to remains high. Can you ensure that you are providing a correct number of SCLK pulses or that there are no any glitches in the SCLK line? 

    Thanks,

    Jellenie

  • Jellenie,

    The AD4115 does not generate a RDY signal for a channel under the following set of conditions:

    1. reset
    2. Set up channel to be differential
    3. Select Bipolar coding
    4. write a 1 to the corresponding FILTER register
    5. Place a positive differential signal on the inputs
    6. Set the ADC mode to continuous conversion
    7. Set the INTERFACE mode to continuous read

    What I observed:

    1. If I place a 5Vpp sine wave on the input, RDY pulses appear when the input is negative. When the input signal is greater than zero, the RDY pulses disappear
    2. If I enable a channel to be SE, it generates a RD pulse correctly
    3. If I select a differential input and Unipolar coding for a channel, the RD pulse appears for positive voltage and negative voltages. But the negative values are zero and the appended status indicates an error - this is the correct behavior.

    If I use Continuous Conversion mode or Single Conversion mode, the RD pulses occur regardless of the input voltage on a differential input. You should be able to replicate my experiment on your end with the eval board and software you have.

    Finally, here is an annotated screenshot of my logic analyzer output with 5Vpp 1KHz sine wave input on channels CH0-CH1, CH2-CH3, CH4-CH5, and CH6-CH7. Note the 500usec gaps in the datastream that occur during the positive half cycle of the sine wave input:

    So, one final question, is it possible I got an early revision of the chip which has since been revised? The markings are:

    [LOGO] AD
    4115BCPZ
    #1939
    47164931
    KOREA

  • 0
    •  Analog Employees 
    on Feb 11, 2021 9:47 AM in reply to WallyBalls

    Hi, 

    Apologies for the delay. But I have tried this on my end and it seems really fine. And as far as I know we also don't have any revision for this product. 

    In terms of the input, I'm not aware that you are applying an AC signal. I would suggest to use a DC type of signal as we haven't specified the part for AC. I'd say it should still work, but I think it might be also easy to check if it is DC. So for example instead of applying a positive half and negative half cycle try to have +10V DC differential input. And then -10V DC differential input. And one more thing, please make sure that you enabled the analog input buffers as I do not see that in the steps above. Though I know you have that steps on the first post. Just making sure that we are not missing anything.  

    Thanks,

    Jellenie

  • Jellenie, I realized that I had the polarity of the SPI clock inverted. Once this was corrected, everything worked correctly.

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