I thought I had this problem figured out but it has returned. I'm using an EVAL-AD4114/15SDZ. Clock is internal and reference is external. SPI clock is 8Mhz.
Steps to reproduce problem:
- Reboot ADC by writing 64 ones to DI pin with CS low
- Wait 1-2msec and raise CS
- Confirm reset by performing read of ID Register
- Write 0x1300 to SETUP0 (Channel 1 is set to measure inputs 0 and 1 differentially after reset but the buffers need to be enabled)
- Write 0x0005 to the FILTER0 register to set the sampling rate to 25,000 SPS
- Write 0x9043 to CHAN1 register to enable, select setup 1, and set the MUX to VIN2, VIN3
- Write 0x1300 to SETUP1
- Write 0x0005 to the FILTER1
- Write 0x0000 to the ADCMODE
- Write 0X00C0 to IFMODE to start continuous read and append status to output
In my code when the RD line goes low I clock in 32 bits. I'm seeing channel 0 on my logic analyzer with valid data followed 145uSec later by another channel 0 reading. If this was working correctly, there would be a new reading every 72.5uSec with channel 0 alternating with channel 1. From the timing, it -looks- like the ADC is doing a conversion on channel 1 but not driving the RD signal. As always, I can send lots of pretty pictures but I think the description is sufficient for now. One other twist to this story: if I set the CHAN1 MUX to VIN3,VIN2, the ADC starts outputting the data from channel 1 - it's the negative of my input but at least it's coming in. I'm getting a little nervous about using this device in my product if a repeatable solution cannot be found.