AD7730 temperature drift about AD conversion data by Master clock

Hello 

I'm DFAE. I have received a question about AD7730 from my customer. According to the customer, temperature drift of AD conversion data using external clock is lager than X'tak and internal clock oscillator. Input signal is DC signal for this test. Bridge was connected same as Figure.24 in AD7730 datasheet. When the temperature was changed from 0 degree C to 40 degree C, output data of ADC was changed about lower 6 bit in 24bit.

Is there an influence of clock type (external or X'tal + internal oscillator) for ADC data when input signal is DC?

Best Regards,

Akira

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  • 0
    •  Analog Employees 
    on Jan 28, 2021 9:48 AM

    Hi Akira,

    Here are few test conditions to be noted before we could narrow down to the exact issue.

    1. Is the customer using EVAL-AD7730 and the application?
    2. Which is the external clock used?
    3. What is the DC input value?
    4. What is the mode of operation?
    5. Is temperature varied from 0 to 40 deg gradually or step?
    6. What is the output data at 0 deg and 40 deg?

    Regards

    Vikas J

  • Hello Vikas,

    The customer used their board not Eval-AD7730. And he used an extarnal X'tal oscillator. 

    The input voltage is 2.5V.

    The mode of operation is Single Conversion Mode.

    Temperature varied is gradually.

    He can't check raw data of  AD7730 output. 

    The customer used AD7730 by internal clock generator in the past their product. This time, the temperature drift of ADC data was gigger than previous product when he try to use AD7730 by extarnal clock. Is there influence of clock type (external or X'tal + internal oscillator) for ADC data when input signal is DC?

    Best Regards,

    Akira

  • +1
    •  Analog Employees 
    on Feb 23, 2021 10:44 AM in reply to AkiraO

    Hi Akira,

    Lot of variables involved. Hence, few more questions.

    1. Could you please provide with the specs/ part no. of external xtal used?
    2. Was the internal excitation clock disabled?
    3. How is the layout for XTAL? is there any ground shielding around XTAL? is XTAL also undergoing temperature change?
    4. What is the source of DC? Is the DC input stable or changed with temperature?
    5. What is the REFIN? Based on the REFIN, the user can compute the actual gain and offset error from the drift specs and identify how much the errors will be added


    Also, what are the other changes made in the new design wrt old design?

    There should not be any influence on the clock type for ADC data.

    Thanks

    Vikas J

  • 0
    •  Analog Employees 
    on Mar 8, 2021 4:30 AM in reply to vikas.jeevannavar

    Hi Akira, 

    May I know the status of this issue. It would be great to answer some questions from Vikas to understand more about what's happening. 

    Ideally, the reference drift would be the most dominating factor. Can you confirm that other than the oscillator did they change the reference part number? It would also be great if you can share the specs of the reference used. 

    Thanks,

    Jellenie

  • Hi Vikas,

    Thak you for your support.

    I comfirmed them to the customer. But the customer decided to use the internal clock oscllator instead of the external one. Then he closed thsi issue. And he also would like to know about the influemce of clock type. I answered your comment. Then this issue wad also closed. 

    Thanks & regards,

    Akira 

  • 0
    •  Analog Employees 
    on Mar 8, 2021 8:08 AM in reply to AkiraO

    Thank you Akira. 

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