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About a waiting time that it takes for SPI communication to be possible after reset the AD2S1210.

We have a question about a waiting time that it takes for SPI communication to be possible after reset the AD2S1210.  

We are trying to start SPI communication (A0=HIGH,A1=HIGH) followed below procedures.

 

1) Output LOW level to /RESET

2. Wait 1ms

3. Output HIGH level to /RESET

4. Wait 20ms

5. Output LOW level to /SAMPLE

6. Output HIGH level to /SAMPLE

7. Output LOW level to /SAMPLE

8. Output HIGH level to /SAMPLE

9. Wait 1ms

10. Start the SPI communication

 

When SPI communication was followed above procedures, we had sent the command information to the SDI pin of the AD2S1210,

but the SDO pin has no any level changes and it was remained LOW level.

However, we tried again the SPI communication after 470ms passed from 10., we had confirmed the level changes on the SDO pin

and the SPI communication become normally.

During the period of 490ms which is a time that after reset till SPI communication become normally,

the output of A remains HIGH level and the output of B remains LOW level, and after 490ms passed, the pulse state is established. 

 

We started SPI communication after the tTRACK time described on P.31 of the reference manual below,

but we couldn't able to start SPI communication without waiting 490ms passed after the reset.

 

https://www.analog.com/media/en/technical-documentation/data-sheets/AD2S1210.pdf

 

Please let us know how to deal this issue.

Thank you for your cooperation!

 

Best regards.

ShinoMasa

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  • ShinoMasa,

    If you are using the AD2S1210 evaluation board there is a device on the HW (ADM811, U8) which is a supervisory device that drives the RESET pin and whose input (outside of the supply, is either the RESET button or the RESET net from J3 pin 19.   This device has a very long reset timeout (on the order of 140-560ms) and this is likely the cause of the interruption in your communication.   You can verify this with a scope to see if the RESET pin to the device is pulled low and the EXC/EXCB is inactive for longer than your input pulse.   The work around is to remove U8 and jumper from the input pin to the RESET output.

    SEan

      

  • SEan,

    Thank you for your reply.
    This time we are not using the AD2S1210 evaluation board.
    The RESET pin on the AD2S1210 is controlled directly from the CPU DO.

    Please check the attached actual waveform.
    After RESET, SAMPLE was output 20ms later, and then SPI communication was started, but SDO did not return.

    If you notice anything, please teach me.

    Best regards.

  • ShinoMasa,

    Thanks for the clarification and the LA capture.   My first question would be are you using WR/FSYNC?  If this is high it would explain why the output driver isn't working.   In Serial mode the WR/FSYNC pin is the effective interface enable NOT CS.   This is a bit confusing but hopefully if you make that quick change in your firmware it will get the interface working for you.

    Sean

  • SEan,
    Thank you for your reply.
    There was a lack of information from me.
    The signal on the WR / FSYNC pin is CS-5.

    I also attached the waveform that was successful after waiting for 490ms and starting SPI communication.


    If you notice anything, please teach me.

    Best regards.
    ShinoMasa

  • ShinoMasa,

    I feel like I'm missing something here.  Can you tell me exactly how you start your sequence.   For instance have the power supply rails been fully established prior to asserting RESET?

    What is the state of RD during initial communication is it tied high?

    Can you please provide a zoomed in version of the communication you are executing when the comms fails after 20ms and then again after 490ms?

    How are the inputs to the RDC biased?  Are you applying a static angle, constant rotation, or other input?

    Looking at your timing may help us get to the bottom of this.

    Sean

  • ShinoMasa,

    I can see your latest reply in email but not in this view.   Can you please resubmit so I can see the images. 

    Thanks


    Sean

  • SEan,
    Thank you for your reply.

    I'm sorry.
    My perception was wrong.

    This chart was the chart obtained on the evaluation board.
    As you answered, it was due to the ADM811's very long reset timeout.

    Thank you for your cooperation in the solution.

    Best regards.
    ShinoMasa

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