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What decides the limit of daisy-chaining of multiple ADCs (AD4007)?


I would like to know the consideration that needs to be taken when daisy-chaining 16 of AD4007.

For example:

1. What is the maximum limit on the number of such (daisy-chained) devices and what all factors decide the limit of the maximum number? Is it possible to daisy-chain 16 of them?

2. What is the minimum SPI clock I need so as not to decrease the sample rate (1MSPS) on all 16 ADCs (16-simultaneous sampling setup)

3. Any extra PCB layout considerations I need to take?

4. I read once that 'SDO drive capability also decides on the limit', could someone comment on that as well?

Thank you.

Added a tag for internal tracking purposes.
[edited by: tschmitt at 1:33 PM (GMT -5) on 19 Jan 2021]