What decides the limit of daisy-chaining of multiple ADCs (AD4007)?


I would like to know the consideration that needs to be taken when daisy-chaining 16 of AD4007.

For example:

1. What is the maximum limit on the number of such (daisy-chained) devices and what all factors decide the limit of the maximum number? Is it possible to daisy-chain 16 of them?

2. What is the minimum SPI clock I need so as not to decrease the sample rate (1MSPS) on all 16 ADCs (16-simultaneous sampling setup)

3. Any extra PCB layout considerations I need to take?

4. I read once that 'SDO drive capability also decides on the limit', could someone comment on that as well?

Thank you.

Added a tag for internal tracking purposes.
[edited by: tschmitt at 1:33 PM (GMT -5) on 19 Jan 2021]
  • +1
    •  Analog Employees 
    on Jan 19, 2021 1:32 PM 1 month ago

    Thanks for your query. I will respond to your individual questions numbered below:

    1. From a functional standpoint there is no upper limit on the maximum number of AD4007 devices you can daisy chain together. While in daisy-chain mode, each AD4007 acts as a simple shift register after clocking out its most recent ADC data, and they continue to do so until the next CNV rising edge, no matter how many SCKs occur. There are some practical limitations though:

    2. To use 16x AD4007s daisy chained together requires clocking out 18 bits * 16 ADCs = 288 SCK periods. In daisy chain mode, the amount of time given to read out data is the CNV period (tcyc) minus the max conversion time spec (tconv). For 1 MSPS, that would be 1us - 320ns = 680ns. So the SCK period would have to be 680ns/288 = 2.3ns which is not supported by the AD4007. The minimum SCK period allowed in daisy chain mode is 20ns to 25ns depending on VIO voltage (see table 2 in the data sheet).

    So in short it isn't actually possible to achieve 1 MSPS for 16x AD4007s operating in one daisy-chain. The equation to calculate the fastest sample rate vs. number of AD4007s would be the following:

    min tcyc = tconv,max spec + (ADC resolution * no. ADCs * min SCK period spec)

    For 16x AD4007s in daisy chain mode, this would be: 320ns + (18 * 16 * 20ns) = 6.8 us, which corresponds to roughly 147 kSPS.

    3. The main layout concern I would have with daisy-chaining 16x ADCs together would be the capacitance on the CNV and SCK traces slowing down their edge rates. This is because you would need to fan out the CNV and SCK signals from the digital host to 16 different devices. To minimize the capacitance, I would recommend placing the devices as close together and as close to the digital host as possible, but you may consider implementing clock buffers as well.

    4. In daisy-chain mode, the SDO of all AD4007s (except for the last one in the chain) are hooked up to the SDI inputs of another AD4007. If those traces are kept relatively short then I don't expect the SDO drive capability to be the limit, especially since the SCK periods in daisy-chain mode are relatively "slow". Again, it comes down to the layout of the PCB and how much capacitance is placed on the SDO outputs as a result but if you keep it to ~20pF or less per device it should be fine.