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External Crystal on AD4115 and EVAL-AD4115SDZ

I just purchased an EVAL-AD4115SDZ so I could evaluate the AD4115. I've noticed that it works as expected after a reset using the internal clock - writing 0x0000 to the ADCMODE register and dropping CS indicates continuous conversions at 125Khz on the RD/MISO pin. But as soon as I write 0x00C0 to the ADCMODE register (enable external clock), the continuous data stream stops. When I look at the CLK test point with my oscilloscope, I am not seeing any oscillation. So my question is: did I receive a defective eval board or is there an undocumented issue with the AD4115. For the record, I also have the AD4112 eval board and the external XTAL oscillator works correctly. 



Fixed typo
[edited by: WallyBalls at 1:58 PM (GMT -5) on 15 Jan 2021]
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  • I can never quite reach zero - my negative values are correct though. Question: if you're using an RPi, then I'm assuming you're using the SPI port on the 40 pin header. If so, are you using Python and SPIDEV? And if you're using SPIDEV, how are you controlling the CS line so that it stays low during continuous read transfers? In fact, could you share your code with me?

  • Strange. Not sure if this is helpful but some of my additional settings for bipolar test was, both input buffers on, external ref, ref+/- buffers off, sinc3_map enabled with odr set to fastest (0x0). Yes, im using the spi port channel 0. !!Interestingly, the aux port will not work in mode 3!! Initially I tried using python and spidev but speeds were very limited. I did not explore continuous read with python/spidev. Am currently running a program in c using pigpio to talk to the adc and dump it to shared memory for further processing in python. For continuous read I have a gpio attached to miso and am blocking for data ready/not ready. In this config the delay between data ready and the first clock pulse is just under 750ns. The blocking is putting one core at 100% but I'm ok with that currently...

  • OK, one difference is that I'm using SINC5 filtering. Is PIGPIO allowing you to continuously hold CS low during the data transfers? SPIDEV can't do that. Are you appending the status byte to the data by setting bit 6 in the IFMODE register?

  • I've no need currently for CS so I just have it tied low. If I did need I would probably just grab another gpio and control it outside of spi with pigpio. I think there is a way to adjust the cs pins in the boot/config.txt file. Could probably shift  or eliminate the linux driver spi cs pins and then control that same pin number with pigpio as a cs if I/O constrained.

  • So, I'm an idiot - based on something you said I realized I had my SPI clock inverted. THAT certainly make a difference. BTW, if you're using the RPi you might want to check out some of my products at pi-plates.com

  • Oh excellent. Happy to hear it's OK. I thought it might be an eval board issue again. I'm now aware of two issues with this board. The external oscillator caps and the 5411 has Ve1 tied to 5V instead of Vio which puts all the side 1 I/O at 5V rather than Vio...    Nice site and good looking boards. If I wasnt keen on building my own rpi daq I might be inclined to grab one of your daq2's. Do you assemble these yourself? It's hard to tell if that microcontroller is a QFN or not. I'm a little nervous I wont be able to solder the LFCSP. I have a "reflow oven" so hopefully that will get me through.

  • I used to build my own in a toaster oven! But now, I get both my prototypes and production runs made in China. Almost all of by uPs are QFPs.

  • Hi Folks, 

    Good to hear that you are both progressing well. Though can you help me Wally to close the two open items regarding your concern. You can just somehow reply how you solved the issue if that won't bother you, so it will help other members in the community that may encounter similar issues. 

    Thanks,

    Jellenie