Do I need to set IOVDD=1.8V to connect the Eval-AD7768FMCZ to an FPGA with 1.8V IO Banks?

I am trying to use the eval-ad7768fmcz with the UltraZed-EG PCIe carrier card with a Ultrazed-EG SOM connected. The FMC IO is connected to 1.8V high performance io.I was wondering if it is necessary to modify the evaluation board to run at 1.8V in order to get it to work.

I tried connecting the board with IOVDD=3.3V and I could see DCLK running, but as soon as I programmed the fpga, DCLK stopped. This led me to the assumption that the incorrect IO voltage was causing the issue. I then modded the board by changing SLP4 to position B to use an external IOVDD and shorted SL18 to connect IOVDD to DGREGCAP, although i am unsure if the latter was necessary since i am applying IOVDD=1.8V externally.

After the mod I measured DCLK to be toggling between 0-1.8V as expected, but I had the same result after programming the fpga and DCLK disappeared once again.

My main question is: Do I need to change IOVDD=1.8V to use the board with 1.8V fpga banks?

If the mods were necessary, were my mods correct? 

I was unsure if changing slp4 to position B was needed if sl18 was shorted, because the DGREGCAP pin might supply the 1.8v, nixing the need for an external 1.8v supply.

However I tried measuring IOVDD with no external supply after sl18 was shorted and did not see 1.8v, so I used an external supply and this is when I could see 1.8v on IOVDD and measured the 1.8v DCLK.

  • 0
    •  Analog Employees 
    on Jan 19, 2021 12:31 AM 1 month ago


    We will look into this, I'll contact the product owner and get back to you.

  • 0
    •  Analog Employees 
    on Jan 20, 2021 11:53 AM 1 month ago


    The IOVDD sets the Logic input output levels for the AD7768 or in other words it sets the Digital interface levels.

    Now if the FMC I/O is operating at 1.8V then the IOVDD needs to be at 1.8V, Figure 75 in the Datasheet shows how to set the IOVDD to 1.8. So we need to short the SL18 on the EVB for setting it so and feed the IOVDD to 1.8V externally. However i was not able to understand the modification of SLP4

    i think the problem you are having is the FMC I/O is not allowing the DRDY to toggle (maybe pulling it low) post programming,  to check this please remove R113 probe the side towards the ADC to see if the DRDY is toggling or not.