synchronization across multiple AD7134 devices

hi

how are you measuring synchronization and how much is it?

how and when is the ODR started - is it consistent and are you sure that PLL is not getting unlocked?

thanks

we have tested with 50 Khz sine wave from an AWG. ODR freqency is 1.25 MHz. The image below shows when delay between adc is 7ns

The image below shows when delay between adc's is 551 ns.

When programming SPI, we are disabling ODR and DCLK input. After programming we  enable ODR and dclk input and then dig_if_reset is enabled. when should the dig_if_reset be given? what should be the status of odr and dclk while giving the dig_if_reset?

thanks for the information.

when do you see 7ns and when do you see 551ns? does it change randomly.

DIG_IF_RESET should be issued simultaneously to both the devices after you give the ODR and DCLK 

thanks

the variations cited above are observed after powering off and powering on the board. Similar observations were also made when we reprogram the  adc through SPI. Once programmed the synchronization value holds and changes only after reprogramming sPI/ resetting the board power. 

DIG_IF_RESET is issued simultaneously to both the devices in our case.

So you say that you get 7ns at the start but once you reprogram the SPI this value changes?

How about the same device channel to channel mismatch? is it always within limits

So you say that you get 7ns at the start but once you reprogram the SPI this value changes?

How about the same device channel to channel mismatch? is it always within limits

hi,

please find reply to your queries in the attachment.

So you say that you get 7ns at the start but once you reprogram the SPI this value changes?

the mismatch changes by reprogramming for spi as well as between power on's of the board.

How about the same device channel to channel mismatch? is it always within limits

The mismatch between channels of same device is withing limits (approx 14 ns)

The dig_if_reset seems to be working but it reduces the device to device mismatch within 180 ns (approx).

The attached screen capture video file shows device to device mismatch to be around (519 ns approx). (This was achieved by programming spi of adc separately and without giving dig_if_reset)

when we give dig_if_reset by giving the spi command. the mismatch reduces to (150ns approx) instead of 10ns.

why does dig_if_reset spi command doesn't reduce the mismatch to stated 10ns? In our case the odr period (sampling interval) is 680ns.   The mismatch before providing dig_if_reset was 519 ns and after  dig_if_reset it was 150 ns. This seems to be the difference of (680ns-519ns) where 680ns is the odr interval/sampling rate.

is the device to device mismatch related to odr frequency/pulse  width?

Hi

Firstly 14ns also looks very high, Spec. on the DS says about 1.5ns,  which we have tested.

Are there are any front end components for the circuit? like driver or so? Are the two inputs physically shorted at the input of ADC?

Coming to Device to Device i see that your phase delay is 520ns and when DIG_RESET is given it switches to 150ns. is this behavior very consistent - meaning on all power ON's its about 500ns and returns to 150ns?

Thanks

hi

There are two ADA8282 amplifiers connected in series to each of the ADC. The 14 ns channel to channel mismatch within adc is probably due to ada8282. since ada8282 channel to channel phase mismatch is 0.33 degree. since our input frequency is 50 khz a phase mismatch of 0.33 degree would correspond to 18ns (approx).

we will test and respond to you shortly for the consistency in behaviour of device to device  mismatch between power on's.

Hi Peria,

May I know the status of this issue? We would like to somehow close and find the solution for this issue. If you find out can you provide it here so someone with a similar issue may find this helpful.

Thanks,

Andrei