synchronization across multiple AD7134 devices

We are using two AD7134 for our acquisition system. To synchronize multiple devices the AD7134 datasheet mentions " SPI to set the DIG_IF_RESET bit to reset the digital interface before the data capture This DIG_IF_RESET command must be given to all the slaves simultaneously using one single SPI write command."

We have set both the AD7134 devices in slave mode and they have independent oscillator for sysclk(MCLK). We program the registers of each device (setting soft reset/frame sel/data mode/other necessary register) independently and then we set dig_if_reset in both the adc by using a common cs signal.  But we are unable to achieve synchronization between the ADC devices. The synchronization is varying for each execution.

Are we missing any sequence in the SPI programming. To cross verify we probed the spi signals of ad7134 evaluation board in cro. There we noticed that following registers are programmed.

register Device 1 Val Device 2 Val
0x02 0xF3 0xF3
0x10 0x02 0x02
0x11 0x50 0x50
0x12 0x02 0x02
0x1F 0x00 0x00
0x1e 0xaa 0xaa
0x18 0x00 not programmed
0x17 0x5D not programmed
0x16 0xC0 not programmed
0x1B 0x00 not programmed
0x1C 0x00 not programmed
0x19 0x00 not programmed
0x1a 0x00 not programmed
0x0F 0x01 not programmed

The dig_if_reset is not at all programmed in the eval board. Request you to clarify on how to achieve synchronization across multiple devices.

Parents Reply
  • we have tested with 50 Khz sine wave from an AWG. ODR freqency is 1.25 MHz. The image below shows when delay between adc is 7ns


    The image below shows when delay between adc's is 551 ns.


    When programming SPI, we are disabling ODR and DCLK input. After programming we  enable ODR and dclk input and then dig_if_reset is enabled. when should the dig_if_reset be given? what should be the status of odr and dclk while giving the dig_if_reset?

  • 0
    •  Analog Employees 
    on Jan 6, 2021 3:08 PM in reply to ppkarupan

    thanks for the information.

    when do you see 7ns and when do you see 551ns? does it change randomly.

    DIG_IF_RESET should be issued simultaneously to both the devices after you give the ODR and DCLK 


  • the variations cited above are observed after powering off and powering on the board. Similar observations were also made when we reprogram the  adc through SPI. Once programmed the synchronization value holds and changes only after reprogramming sPI/ resetting the board power. 

    DIG_IF_RESET is issued simultaneously to both the devices in our case.

  • 0
    •  Analog Employees 
    on Jan 22, 2021 6:58 AM in reply to ppkarupan

    So you say that you get 7ns at the start but once you reprogram the SPI this value changes?

    How about the same device channel to channel mismatch? is it always within limits

  • hi,

    please find reply to your queries in the attachment.

    So you say that you get 7ns at the start but once you reprogram the SPI this value changes?

    the mismatch changes by reprogramming for spi as well as between power on's of the board.

    How about the same device channel to channel mismatch? is it always within limits

    The mismatch between channels of same device is withing limits (approx 14 ns)

    The dig_if_reset seems to be working but it reduces the device to device mismatch within 180 ns (approx).

    The attached screen capture video file shows device to device mismatch to be around (519 ns approx). (This was achieved by programming spi of adc separately and without giving dig_if_reset)

    when we give dig_if_reset by giving the spi command. the mismatch reduces to (150ns approx) instead of 10ns.

    why does dig_if_reset spi command doesn't reduce the mismatch to stated 10ns? In our case the odr period (sampling interval) is 680ns.   The mismatch before providing dig_if_reset was 519 ns and after  dig_if_reset it was 150 ns. This seems to be the difference of (680ns-519ns) where 680ns is the odr interval/sampling rate.

    is the device to device mismatch related to odr frequency/pulse  width?

  • 0
    •  Analog Employees 
    on Feb 16, 2021 1:34 PM in reply to ppkarupan


    Firstly 14ns also looks very high, Spec. on the DS says about 1.5ns,  which we have tested.

    Are there are any front end components for the circuit? like driver or so? Are the two inputs physically shorted at the input of ADC?

    Coming to Device to Device i see that your phase delay is 520ns and when DIG_RESET is given it switches to 150ns. is this behavior very consistent - meaning on all power ON's its about 500ns and returns to 150ns?